Novena EVT to DVT changes
- 1 Novena EVT to DVT changes
- 1.1 ECO1: Inrush current limit
- 1.2 ECO2: FPGA boot fuse interference
- 1.3 ECO3: Gbit Ethernet Reset
- 1.4 ECO4: PCIe power on
- 1.5 ECO5: Improve magnetics termination
- 1.6 ECO6: Gbit reflcock SI
- 1.7 ECO7: HDMI HPD polarity
- 1.8 ECO8: Audio chip sucks (power)
- 1.9 ECO9: Reset pulse too short
- 1.10 ECO10: Input cap bleed
- 1.11 ECO11: Split audio record/playback clocks
- 1.12 ECO12: Add user switch on bottom side
- 1.13 ECO13: Reduce attack surface by making DDC_SCL unidirectional
- 1.14 ECO 14: Fix L11N footprint
- 1.15 ECO 15: Drop silicon mic feature
- 1.16 ECO 16: Drop Raspberry Pi header
- 1.17 ECO17: Refactor LCD connector
- 1.18 ECO18: Move status LED
- 1.19 ECO19: Refactor blinkenlight header
- 1.20 ECO20: Make LCD off-state bleed stronger
- 1.21 ECO21: Upgrade FPGA and power supply
- 1.22 ECO22: Remove low-speed FPGA ADC
- 1.23 ECO23: Remove low-speed digital I/O
- 1.24 ECO24: Remove PWM I/O
- 1.25 ECO25: Remove I2C FPGA ROM
- 1.26 ECO26: Add DDR3 memory to FPGA
- 1.27 ECO27: Add high-speed expansion header to FPGA
- 1.28 ECO 28: Remove CCLK terms
- 1.29 ECO 29: Add DDR3 VREF options
- 1.30 ECO 30: SATA power cap interferes with expansion port
- 1.31 ECO 31: Remove FPGA Done LED
- 1.32 ECO 32: Add power switch to FPGA expansion card
Novena EVT to DVT changes
This is a list of all the changes applied to the board from EVT1A to DVT1 release. If it's not on this list, it didn't happen.
Each change has the format of issue summary/resolution, and specific change
ECO1: Inrush current limit
The RC constant governing the turn-on/turn-off rates of the FET power switches needs tuning. In EVT, most switches are turning on too quickly for them to be effective. Resolution is to increase capacitance and resistance.
|R38N 330, 1% / REC1005N||R38N 10k, 1% / RESC1005N||P3.3V_DELAYED|
|C30N 0.1uF, 6.3V, X5R / CAPC0603N_B||C30N 1.0uF, 25V, 20% X5R / CAPC1608N||P3.3V_DELAYED|
|R29N 330, 1% / REC1005N||R29N 10k, 1% / RESC1005N||P5.0V_DELAYED|
|C27N 0.1uF, 6.3V, X5R / CAPC0603N_B||C27N 1.0uF, 25V, 20% X5R / CAPC1608N||P5.0V_DELAYED|
|R11H 330, 1% / REC1005N||R11H 10k, 1% / RESC1005N||SATA_PWRON|
|C10H 0.1uF, 6.3V, X5R / CAPC0603N_B||C10H 1.0uF, 25V, 20% X5R / CAPC1608N||SATA_PWRON|
|C10X 0.1uF, 6.3V, X5R / CAPC0603N_B||C10X 1.0uF, 25V, 20% X5R / CAPC1608N||PCIE_PWRON|
|R15L 1k, 1% / REC1005N||R15L 10k, 1% / RESC1005N||LCD_VCC_SW|
|C14L 0.1uF, 6.3V, X5R / CAPC0603N_B||C14L 1.0uF, 25V, 20% X5R / CAPC1608N||LCD_VCC_SW|
|C19L 0.1uF, 25V, X5R / CAPC1005N||C19L 1.0uF, 25V, 20% X5R / CAPC1608N||LCD_BL_VDD|
ECO2: FPGA boot fuse interference
FPGA's internal pull-ups on boot will yank boot fuses to the CPU, causing wrong boot source to be selected.
|R12F 4.7k, 1% / REC1005N||R12F 4.7k, 1% (DNP) / RESC1005N||depop pull-down|
|R13F 4.7k, 1% (DNP) / REC1005N||R13F 4.7k, 1% / RESC1005N||populate pull-up|
ECO3: Gbit Ethernet Reset
Default circuit recommended by reference design is bogus. Get rid of it.
|C32G 10uF, 10V, X5R, 20%||removed|
|R20G 10k, 1%||R20G 10k, 1% (DNP)||also changed to pull to ground by default|
ECO4: PCIe power on
Wire PCI express power on line (gate of Q10X) to ball R1 / pad name GPIO_17 / "GPIO7 aka 6 * 32 + 12 = GPIO 204". Software change required
ECO5: Improve magnetics termination
The magnetics in the PHY are not terminated properly, causing ISSI.
|R14G 0 ohm||R14G 0 ohm (DNP)||also move EN1G_3.3VA line to other side of decaps on CT|
ECO6: Gbit reflcock SI
Drive strength of U10G is not strong enough to overcome series terminator. Replace with shunt. Add RC shunt terminator at the end of the transmission line instead.
|R21G 49.9, 1% RESC1005N||R21G 0 ohm RESC1005N|
|none||R20S 49.9 1%|
|none||C16S 2200pF, X7R, 50V, 10%||cap needs tuning|
ECO7: HDMI HPD polarity
HDMI HPD polarity is not software programmable, so need to buffer (not invert) incoming signal.
|R28L 0 ohm||R28L 0 ohm (DNP)|
|R27L 0 ohm (DNP)||R27L 0 ohm|
|Q17L 2N7002W (DNP)||Q17L 2N7002W|
|R29L 10k, 1% (DNP)||R29L 10k, 1%|
ECO8: Audio chip sucks (power)
During power down, audio chip totally leaks power through the I2C bus. Need to really strengthen the pull-down to fully reset the chip and fight the pull-ups on I2C.
|R21A 100, 1%||R21A 20 ohms, 1%,0402||10 ohm on EVT1A, but should be effective at 20 ohms. 10 ohms would be a new component, if lower value is needed go to 8.06 1% (from R10N)|
ECO9: Reset pulse too short
The PFUZE PMIC reset cycle is too short, approx 2 ms after VGEN6 (last supply) rises. Since there are other supplies slaved off of VGEN5/6 enables stabilizing, reset pulse needs to be lengthened. Use a standard reset monitor on the +5V line, which ensures a minimum 100ms total reset pulse width from 5V stable; provides plenty of margin for system to stabilize (~50ms or so).
|(none)||U14N APX803-44-SAG-7 or RT9818CXXGVL 4.2V-4.38V setpoint||multiple parts can serve this role|
|(none)||C33N 0.1uF, 25V, X5R|
ECO10: Input cap bleed
If there is an error condition on U11N, the chip goes into shut down. The leakage in protect mode is sufficiently small that it takes several seconds for the input caps to bleed down to a point where the error condition is cleared. This can lead to a bad user experience. For fixed installations, a 2.2k resistor is installed to bleed current on the input. This wastes about 65mW of power, but the capacitors now discharge in under a second. For battery/mobile installations, the resistor should *not* be installed, and instead the battery board should either guarantee sufficient time for a power cycle or there should be a switched pull-down on the battery board side to clear the error condition.
|(none)||R31N 2.2k, 1%|
ECO11: Split audio record/playback clocks
The audio codec requires independent clocks for record and playback (in part to allow for dissimilar sample rates during full duplex operation).
- ALRCK is connected to what is currently LCD_BL_ON
- LCD_BL_ON is connected to what is currently KEY_ROW4
- User switch is no longer bridging GPIOs, it's now a button shorting a pull-up to ground
|(none)||R15S 10k, 1%||software change required -- key col4 is normally pulled up, and goes low when user switch is hit|
|(none)||C15S 0.1uF, 6.3V, X5R|
ECO12: Add user switch on bottom side
Add a user switch (mirror image) on bottom side of PCB to be compatible with new ID
|(none)||SW11S TS-1187A, Chi Fung|
ECO13: Reduce attack surface by making DDC_SCL unidirectional
HDMI DDC and PMIC share the same I2C bus. This means that a hostile HDMI device could commandeer the I2C bus and attempt to reprogram the PMIC with values that can potentially cause permanent damage to the board. Prevent this by turning the DDC device into a slave only. This is accomplished by changing the level shifter on the bus into a unidirectional buffer. This prevents the trivial attack scenario on the board, where a programmable I2C interface on an HDMI plug could be used to destroy a Novena (i.e., a simple software patch loaded into certain TV sets (particularly ones that grab updates via the internet) could accomplish this). Instead, a custom I2C-busting device (like an NeTV or bus pirate) must be made and physically connected to attack Novena using the remaining attack surface.
The remaining attack surface consists of monitoring the SCL/SDA lines and attempting to modify the I2C bus on-the-fly by overriding the SDA line's value using a very strong driver. This can be accomplished by simply waiting for any transaction on the bus where SCL is toggled, and modifying both the destination address and data packets (this is done by an NeTV, for example). One countermeasure is to disable all traffic to the PMIC's I2C bus as long as an HDMI device is plugged in. This is not a totally unreasonable scenario, as it basically means the device is locked in the "on" state if it's driving an external projector.
Of course, if someone had it about them to break into your office and mod the I2C lines in your HDMI interface to your external monitor, they probably could just as easily smash your laptop, mod your AC adapter, or mess with your USB cables and cause you similar trouble. So I think this remaining attack surface is comparable to other existing attack surfaces, and therefore not a high priority to button up.
|(none)||R33L 47k, 1%||set to a high value to prevent leakage, but should still be fast enough for I2C use|
ECO 14: Fix L11N footprint
Footprint for L11N was mistakenly set to MSS1048; should be sized for XAL4020.
|L11N Wurth 7447797050 0.50uH 8.5A / COILCRAFT_MSS1048||L11N Coilcraft 0.60uH 10.4A XAL4020-601ME / COILCRAFT_XAL4020|
ECO 15: Drop silicon mic feature
Silicon mic built-into motherboard is being dropped. If a microphone is required, one must plug in an android or iphone compatible hands-free headset that contains a mic. The silicon mic is dropped in part due to privacy concerns.
Note that connector to support an add-on board for an external silicon mic is still provisioned.
|U13A MP34DT01||U13A MP34DT01 (DNP)|
ECO 16: Drop Raspberry Pi header
No value is seen in keeping the Rpi header; it takes a lot of space, has an inferior pin-out, and probably nobody will actually use it. The board space will instead be allocated to a new header that more intelligently uses the high-speed differential pairs available on the FPGA for expansion and prototyping.
|P13D Male 13x2 2.54mm header||(none)|
|C13D 0.1uF, 25V, X5R||(none)|
|C12D 0.1uF, 25V, X5R||(none)|
ECO17: Refactor LCD connector
Instead of relying on a discrete-wire cable, flex circuit headers will be used to connect to the LCD. These are cheaper and easier to make in small quantities than the discrete-wire cables. This enables a multiplicity of displays to be adapted to the board with a lower overhead cost.
- Wire up LVDS0_TX3_[N,P] and LVDS1_TX3_[N,P] to support 8-bit color depths on all channels (better banding performance on IPS displays)
- Remove resistive touch screen headers and merge signals into FFC breakout
- Due to high signal speeds, minimize FFC length, and use local adapter/repeater board for super high resolution displays
|JP10L HRS FX15S-41S-0.5SH||Molex 51296-5494 or equiv|
|P14D AMP 487951-4||removed||merged into JP10L|
|P15D Male 2.5mm 4x1 right-angle header (DNP)||removed|
ECO18: Move status LED
Status LED needs to be moved to edge of board and made right-angle for compatibility with router-case ID
|D14D APT1608SGC||D14D LTST-270KGKT||same color (green), changed to right angle|
ECO19: Refactor blinkenlight header
A small header is provided for general-purpose switches and blinkenlight for miscellaneous case integration needs. Currently, there is no solid requirement driving the needs of the header. However, the header is occupying a very valuable routing channel.
Change header from through-hole to surface-mount, and reduce pin count to something more likely needed (6 total I/Os)
- Remove key_row4/key_col4 pins
- ECSPI3_RDY signal removed (not needed due to no Rpi header)
- P16D TS_ANA wired up to header (just so we have one "housekeeping" analog input available, e.g. for light sensor or temp sensor)
|P16D Male 8x2 2.54mm||P16D HRS F19SC-8S-0.5SH|
ECO20: Make LCD off-state bleed stronger
Experience with the audio codec indicates existing 330 ohm resistor is probably too weak to fight substantial leakage.
|R17L 330, 1%||49.9, 1%|
ECO21: Upgrade FPGA and power supply
Upgrade FPGA from Spartan 6 LX9 to LX45 -- enable more application such as digital oscope, logic analyzer, SDR, etc.
Upgrade capability of FPGA 1.2V VCCINT supply from 1A to 2A -- in anticipation of larger, more complex FPGA designs.
|U800 XC6SLX9-2CSG324C||U800 XC6SLX45-3CSG324C||supports 800MT/s DDR3, larger capacity for more fun!|
|U10F LMR10510YSD||U10F LMR10520YSDE|
|L10F 2.2uF, coilcraft MSS5121-22ML||2.2uH, coilcraft MSS5131-222ML||same 2.3A max current, slight upgrade in Irms|
|D11F CDBM140-G||D11F CDBMT220L-G||same footprint|
|R19F 10k, 1%||R19F 10.5k, 1%||increase Vccint of FPGA to allow for 800MT/s DDR3|
|C65F 4.7uF, 10V, X5R, 10%||C65F 10uF, 10V, X5R, 20%||both CAPC1608N|
|C62F, C63F 10uF, 10V, X5R, 20% CAP1608N||C62F, C63F 22uF, 6.3V, X5R, 20% CAPC1608N_HD|
ECO22: Remove low-speed FPGA ADC
Making room for the hyperspace bypass. Actually, just a dual, 8-bit 800MSPS ADC. Or a single 12-bit 800MSPS ADC. Or another low-speed ADC, if you care.
|R28F 10k, 1%||removed|
|C68F 4.7uF, 10V, X5R, 10%||removed|
|C69F 0.1uF, 25V, X5R||removed|
|C67F 0.1uF, 6.3V, X5R||removed|
|C70F 4.7uF, 10V X5R, 10%||removed|
|C71F 0.1uF, 25V X5R||removed|
|D13F, D16F RCLAMP0524P||removed|
|RP10F, RP13F 220/RP||removed|
|P11F Female 8x1 2.54mm header||removed|
|P12F Female 8x2 2.54mm header||removed|
|C72F 1.0uF, 25V, 20% X5R||removed|
|R28A 0 ohm (DNP)||removed||no longer relevant since VANA removed in this ECO|
ECO23: Remove low-speed digital I/O
Removed in favor of routing a dozen high-speed capable digital I/O to a high-speed header.
|D17F, D14F RCLAMP0524P||removed|
|RP11F, RP14F 22/RP||removed|
|P13F Female 8x1 2.54mm header||removed|
|P14F Female 8x2 2.54mm header||removed|
|C73F 1.0uF, 25V, 20% X5R||removed|
ECO24: Remove PWM I/O
Removed in favor of routing a dozen high-speed capable digital I/O to a high-speed header.
|D19F, D15F RCLAMP0524P||removed|
|RP12F, RP15F 220/RP||removed|
|P15F Female 8x2 2.54mm header||removed|
|P16F Female 8x1 2.54mm header||removed|
|P_PWM 2 pin 1.27mm male header||removed|
|C74F 1.0uF, 25V, 20% X5R||removed|
ECO25: Remove I2C FPGA ROM
The I2C FPGA ROM is deemed redundant with the SPI option. The SPI option allows for a higher capacity part that costs about the same. Also, there is no clear requirement for this part, it's simply available "just in case".
|R29F, R30F 2.2k, 1%||removed|
|P_LI2C_WP 2 pin 1.27mm male header||removed|
ECO26: Add DDR3 memory to FPGA
Adding a local DDR3 memory device to the FPGA. Trying for a 16-bit part so total B/W capable is 1.6 GB/s, sufficient for buffering high-speed ADC capture traces, etc.
Some signals are moved to a new bank:
- AUD_MCLK displaced
- EPIT_EPIT0 displaced
- CLK2_P/_N displaced to bank 2
- UIM_PWR displaced
- FPGA_LED2 displaced
- DDC_SCL, DDC_SDA displaced
- RESETB_MCU displaced
In addition, C15F-C21F capacitors changed from 3.3V to 1.5V rails, as bank 1 is now a 1.5V VCCIO bank.
|(none)||U12F MT41J128M16HA-125||128M x 16 bit wide DDR3 -- 2 Gbits total|
|(none)||R28F 100, 1%|
|(none)||R31F 100, 1% (DNP)||just in case a clock tuning is needed|
|(none)||R32F 4.7k, 1%|
|(none)||R34F 240, 1% added|
|(none)||R33F 4.7k, 1% added|
|(none)||C72F-C80F and C84F-C91F 0.1uF, 6.3V X5R 0201||note multiple P/Ns|
|(none)||C70F 1.0uF, 25V 20% X5R added|
|(none)||C71F, C67F 10uF, 10V X5R 20% added|
|(none)||C68F, C69F 0.1uF, 6.3V X5R 0201 added|
ECO27: Add high-speed expansion header to FPGA
Add header capable of high-speed differential (Gbit-speeds) expansion to the FPGA.
Power is provisioned at 1.5A @ 5V. Intention is for expansion card to have local power converters from the 5V line.
- 16 high-speed LVDS-capable data lines
- 2 high-speed LVDS clock lines
- 2 high-speed LVDS status lines (e.g. for overflow signal)
- approx 16-20 digital lines, intended for single-ended use. These are for configuring the high speed ADC, input voltage range, and also to serve as inputs for logic analysis purposes.
- All I/Os can be configured, inside the FPGA, as low-speed 3.3V-capable digital I/O.
The goal is to support up to two channels 8-bit 800MSPS+ data capture, plus 8+ lines of logic analysis (ideally 16, but depends on routability). Since it's an add-on card, this could also be configured as a single 12-bit 800MSPS+ data capture with more digital I/O.
|(none)||JP10F FX10A-80S/SV(**)||Receptacle on mainboard, so 4mm or 5mm header can be put on the daughtercard. Rated to 10 GHz.|
|(none)||C82F 10uF, 10V, X5R, 20%|
|(none)||C83F 0.1uF, 25V, X5R|
ECO 28: Remove CCLK terms
CCLK is greatly shortened due to removal of Rpi header. Trace length is now just 750 mils. Termination is no longer needed.
|R10F, R11F 100, 1%||removed|
ECO 29: Add DDR3 VREF options
Add option to generate DDR3 VREF locally, improve bypassing of the lines.
|(none)||C92F, C93F 0.1uF, 6.3V, X5R|
|(none)||C94F 1.0uF, 25V, 20%, X5R|
|(none)||R10F 0ohm, 0805||depopulate for local VREF|
|(none)||R11F, R29F 1k, 1% (DNP)||populate for local VREF|
ECO 30: SATA power cap interferes with expansion port
The 220uF bulk decap on SATA switched power port is too tall; it prevents a daughtercard from mounting for the FPGA expansion.
Replace with a pair of 22uF caps. This decision was made because (a) I don't like tantalums (b) getting another unique low-profile aluminum cap into inventory would be expensive and (c) as long as we're using SSDs I think we should be fine with 50uF total capacitance on the line. The big cap is questionably necessary, and if so, probably only for spinning disks.
|(none)||C22H 22uF,10V, X5R, 20%|
|C11H 220uF, 10V, VS D||C11H 22uF, 10V, X5R, 20%|
ECO 31: Remove FPGA Done LED
Ain't nobody got time fo' that.
Seriously, though, they don't. It's not even populated and it's in the way.
|Kingbright APT1608SGC green (DNP)||removed|
|R22F 330, 1%||R22F 4.7k, 1%|
ECO 32: Add power switch to FPGA expansion card
In standby/hibernate modes, we probably want to be able to turn off the power-hungry analog front ends on the expansion slot. Add a power switch that defaults to 'on', but wired to CPU to give an option to power down the expansion card.
software change required: Power enable is wired to SD1_DAT1 / ball C20.
|(none)||R35F 10k, 1%|
|(none)||R36F 10k, 1%|
|(none)||R30F 100k, 1%|
|(none)||C95F 1.0uF, 25V, 20% X5R|