Difference between revisions of "Novena EVT to DVT changes"
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| − | == FPGA boot fuse interference== | + | == ECO2: FPGA boot fuse interference== |
FPGA's internal pull-ups on boot will yank boot fuses to the CPU, causing wrong boot source to be selected. | FPGA's internal pull-ups on boot will yank boot fuses to the CPU, causing wrong boot source to be selected. | ||
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Revision as of 10:09, 19 March 2013
Contents
Novena EVT to DVT changes
This is a list of all the changes applied to the board from EVT1A to DVT1 release. If it's not on this list, it didn't happen.
Each change has the format of issue summary/resolution, and specific change
ECO1: Inrush current limit
The RC constant governing the turn-on/turn-off rates of the FET power switches needs tuning. In EVT, most switches are turning on too quickly for them to be effective. Resolution is to increase capacitance and resistance.
| EVT | DVT | Notes |
|---|---|---|
| R38N 330, 1% / REC1005N | R38N 10k, 1% / RESC1005N | P3.3V_DELAYED |
| C30N 0.1uF, 6.3V, X5R / CAPC0603N_B | C30N 1.0uF, 25V, 20% X5R 0201 / CAPC0603N_B | P3.3V_DELAYED |
| R29N 330, 1% / REC1005N | R29N 10k, 1% / RESC1005N | P5.0V_DELAYED |
| C27N 0.1uF, 6.3V, X5R / CAPC0603N_B | C27N 1.0uF, 25V, 20% X5R 0201 / CAPC0603N_B | P5.0V_DELAYED |
| R11H 330, 1% / REC1005N | R11H 10k, 1% / RESC1005N | SATA_PWRON |
| C10H 0.1uF, 6.3V, X5R / CAPC0603N_B | C10H 1.0uF, 25V, 20% X5R 0201 / CAPC0603N_B | SATA_PWRON |
| C10X 0.1uF, 6.3V, X5R / CAPC0603N_B | C10X 1.0uF, 25V, 20% X5R 0201 / CAPC0603N_B | PCIE_PWRON |
| R15L 1k, 1% / REC1005N | R15L 10k, 1% / RESC1005N | LCD_VCC_SW |
| C14L 0.1uF, 6.3V, X5R / CAPC0603N_B | C14L 1.0uF, 25V, 20% X5R 0201 / CAPC0603N_B | LCD_VCC_SW |
| C19L 0.1uF, 25V, X5R / CAPC1005N | C19L 1.0uF, 25V, 20% X5R 0201 / CAPC0603N_B | LCD_BL_VDD |
ECO2: FPGA boot fuse interference
FPGA's internal pull-ups on boot will yank boot fuses to the CPU, causing wrong boot source to be selected.
| EVT | DVT | Notes |
|---|---|---|
| R12F 4.7k, 1% / REC1005N | R12F 4.7k, 1% (DNP) / RESC1005N | depop pull-down |
| R13F 4.7k, 1% (DNP) / REC1005N | R13F 4.7k, 1% / RESC1005N | populate pull-up |
Gbit Ethernet Reset
Default circuit recommended by reference design is bogus. Get rid of it.
| EVT | DVT | Notes |
|---|---|---|
| C32G 10uF, 10V, X5R, 20% | removed | |
| D11G BAT54T1G | removed | |
| D12G BAT54T1G | removed | |
| R20G 10k, 1% | R20G 10k, 1% (DNP) | also changed to pull to ground by default |
- remove R11X, tie gate of Q10X to P3.3V_DELAYED (off of pin 2 of Q11X) (resolve PCIE power on issue)
- remove R14G (possibly resolve magnetics termination issue)
- replace R21G with 0-ohm resistor or shunt (partially resolve Gbit refclock stability issue)
- move R28L to R27L (HDMI HPD swap)
- add Q17L (HDMI HPD swap)
- add R29L (HDMI HPD swap)
- change R21A from 100 ohms to 10 ohms (see if others need changing)
- APX803-44SAG-7 added, monitoring the P5.0V line, and pulling down the RESETBMCU line.
- add 2.2k resistor in shunt with input capacitor network (BATT_PWR to ground)
- Cut ALRCK trace to U11A, and jumper pin 9 of U11A to LCD_BL_ON
- Rewire LCD_BL_ON to a new GPIO on the i.MX6 (final GPIO TBD)
- Connect PICE_PWRON to i.MX6 (final GPIO TBD)
