Novena EVT to DVT changes

Novena EVT to DVT changes

This is a list of all the changes applied to the board from EVT1A to DVT1 release. If it's not on this list, it didn't happen.

Each change has the format of issue summary/resolution, and specific change

Inrush current limit

The RC constant governing the turn-on/turn-off rates of the FET power switches needs tuning. In EVT, most switches are turning on too quickly for them to be effective. Resolution is to increase capacitance and resistance.

EVT	DVT	Notes
R38N 330, 1% / REC1005N	R38N 10k, 1% / RESC1005N	P3.3V_DELAYED
C30N 0.1uF, 6.3V, X5R / CAPC1005N	C30N 1.0uF, 25V, 20% X5R 0201 / CAPC1005N	P3.3V_DELAYED
R29N 330, 1% / REC1005N	R29N 10k, 1% / RESC1005N	P5.0V_DELAYED
C27N 0.1uF, 6.3V, X5R / CAPC1005N	C27N 1.0uF, 25V, 20% X5R 0201 / CAPC1005N	P5.0V_DELAYED

• R12F to DNP, R13F to 4.7k, 1% 0402 (resolve boot fuse issue with FPGA pull-ups)
• remove C32G, D12G, R20G, D11G; short across D12G with wire jumper or 0805 resistor, 0 ohm (resolve gbit ethernet reset issue)
• remove R11X, tie gate of Q10X to P3.3V_DELAYED (off of pin 2 of Q11X) (resolve PCIE power on issue)
• remove R14G (possibly resolve magnetics termination issue)
• replace R21G with 0-ohm resistor or shunt (partially resolve Gbit refclock stability issue)
• move R28L to R27L (HDMI HPD swap)
• add Q17L (HDMI HPD swap)
• add R29L (HDMI HPD swap)
• change R21A from 100 ohms to 10 ohms

• APX803-44SAG-7 added, monitoring the P5.0V line, and pulling down the RESETBMCU line.
• probably all instances of RC timing for power switches need to be improved (see 10k/1uF patch)
• add 2.2k resistor in shunt with input capacitor network (BATT_PWR to ground)
• Cut ALRCK trace to U11A, and jumper pin 9 of U11A to LCD_BL_ON
• Rewire LCD_BL_ON to a new GPIO on the i.MX6 (final GPIO TBD)
• Connect PICE_PWRON to i.MX6 (final GPIO TBD)