GPBB User Guide

The GPBB is a good entry point for most hardware hacking applications on Novena. This document describes in some detail about the function and theory of operation behind the GPBB.

GPBB Features

• Digital I/O
  • 16 digital outputs organized in two 8-bit banks (A and B)
  • Each bank can be individually tri-stated
  • 8 digital inputs organized in a single 8-bit bank
• Switchable I/O voltage
  • I/O VDD software switchable between +5V and a lower voltage
  • Lower voltage I/O VDD nominally set to 3.3V but adjustable changing out a single resistor
  • I/O VDD current-limited to 500mA
  • In 5V mode, overcurrent indicator available
  • I/O VDD can be sampled by on-board ADC to verify operation
• LEDs
  • Four green LEDs
  • Connected to port B bits 0-3
• Analog Input
  • 6x 10-bit analog inputs
  • 0-4.7V full scale range
  • AVDD set by local LDO to +/- 1.5% accuracy
  • Up to 200 ksps conversion rate
  • Upgradable to 12-bit accuracy by swapping out ADC chip
  • DAC-to-ADC loopback and VDD/IO measurement paths available
• Analog output
  • 2x 10-bit analog outputs
  • 0-3.3V full scale range
  • Output speed limited by I2C bus rate (100kHz I2C -> ~5kHz output rate)
  • Upgradable to 12-bit accuracy by swapping out DAC chips

GPBB Host Interface Features

The host interface to the GPBB is implemented using the FPGA. It is configurable, and therefore, this feature list should not be considered etched in stone. There is a lot of flexibility on how to implement the host interface, and this particular configuration was chosen to maximize the pedagogical value of the GPBB reference design.

• EIM register interface
  • Modular, scalable register interface
  • FPGA version reporting
  • Loopback testing
  • Control of the digital input and output ports
• CPU-> FPGA I2C register interface
  • Example of communicating with the FPGA via I2C
  • Control and readout of the ADC
  • FPGA version reporting
  • Loopback testing
• CPU->DAC I2C interface
  • Direct bus interface to I2C with expansion card components
  • Example of using expansion port with no FPGA intervention
  • 2x DAC chips connected to CPU I2C bus

Block Diagram

Hardware Photo

Note R12, the voltage set resistor, is in the mid-left of the board in this photo.

Setting the I/O Voltage

The low voltage setting for the I/O is defaulted to 3.3V.

You can change this by desoldering R12, the larger 1206 resistor, and replacing it with one of the following:

• 316 ohm for 3.3V (default)
• 215 ohm for 2.5V
• 124 ohm for 1.8V

If you don't want to desolder the 316 ohm resistor, you can:

• Parallel a 680 ohm resistor with the default 316 ohm resistor to get 215 ohms
• Parallel a 200 ohm resistor with the default 316 ohm resistor to get 122 ohms

The 1206 resistor is large enough so one can fairly easily parallel an axial resistor across the surface-mount device.