Difference between revisions of "GPBB User Guide"
(Created page with "The GPBB is a good entry point for most hardware hacking applications on Novena. This document describes in some detail about the function and theory of operation behind the GPBB...") |
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** Upgradable to 12-bit accuracy by swapping out DAC chips | ** Upgradable to 12-bit accuracy by swapping out DAC chips | ||
| − | =GPBB | + | =GPBB Host Interface Features= |
| − | The | + | The host interface to the GPBB is implemented using the FPGA. It is configurable, and therefore, this feature list should not be considered etched in stone. There is a lot of flexibility on how to implement the host interface, and this particular configuration was chosen to maximize the pedagogical value of the GPBB reference design. |
* EIM register interface | * EIM register interface | ||
** Modular, scalable register interface | ** Modular, scalable register interface | ||
| Line 35: | Line 35: | ||
** Loopback testing | ** Loopback testing | ||
** Control of the digital input and output ports | ** Control of the digital input and output ports | ||
| + | * CPU-> FPGA I2C register interface | ||
| + | ** Example of communicating with the FPGA via I2C | ||
** Control and readout of the ADC | ** Control and readout of the ADC | ||
| − | * I2C | + | ** FPGA version reporting |
| − | ** | + | ** Loopback testing |
| + | * CPU->DAC I2C interface | ||
| + | ** Direct bus interface to I2C with expansion card components | ||
| + | ** Example of using expansion port with no FPGA intervention | ||
| + | ** 2x DAC chips connected to CPU I2C bus | ||
Revision as of 13:59, 2 November 2014
The GPBB is a good entry point for most hardware hacking applications on Novena. This document describes in some detail about the function and theory of operation behind the GPBB.
GPBB Features
- Digital I/O
- 16 digital outputs organized in two 8-bit banks (A and B)
- Each bank can be individually tri-stated
- 8 digital inputs organized in a single 8-bit bank
- Switchable I/O voltage
- I/O VDD software switchable between +5V and a lower voltage
- Lower voltage I/O VDD nominally set to 3.3V but adjustable changing out a single resistor
- I/O VDD current-limited to 500mA
- In 5V mode, overcurrent indicator available
- I/O VDD can be sampled by on-board ADC to verify operation
- LEDs
- Four green LEDs
- Connected to port B bits 0-3
- Analog Input
- 6x 10-bit analog inputs
- 0-4.7V full scale range
- AVDD set by local LDO to +/- 1.5% accuracy
- Up to 200 ksps conversion rate
- Upgradable to 12-bit accuracy by swapping out ADC chip
- DAC-to-ADC loopback and VDD/IO measurement paths available
- Analog output
- 2x 10-bit analog outputs
- 0-3.3V full scale range
- Output speed limited by I2C bus rate (100kHz I2C -> ~5kHz output rate)
- Upgradable to 12-bit accuracy by swapping out DAC chips
GPBB Host Interface Features
The host interface to the GPBB is implemented using the FPGA. It is configurable, and therefore, this feature list should not be considered etched in stone. There is a lot of flexibility on how to implement the host interface, and this particular configuration was chosen to maximize the pedagogical value of the GPBB reference design.
- EIM register interface
- Modular, scalable register interface
- FPGA version reporting
- Loopback testing
- Control of the digital input and output ports
- CPU-> FPGA I2C register interface
- Example of communicating with the FPGA via I2C
- Control and readout of the ADC
- FPGA version reporting
- Loopback testing
- CPU->DAC I2C interface
- Direct bus interface to I2C with expansion card components
- Example of using expansion port with no FPGA intervention
- 2x DAC chips connected to CPU I2C bus
