Revision history of "NeTV FPGA architecture"

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  • (cur | prev) 16:38, 2 November 2011Bunnie (talk | contribs). . (17,160 bytes) (+17,160). . (Created page with "=Development Background= NeTV's FPGA source is written in Verilog, and is compiled using Xilinx ISE tools. The freely available Webpack download will compile the code for the Spa...")