Novena FPGA Expansion

From Studio Kousagi Wiki
Revision as of 05:03, 7 August 2014 by Tom McLeod (talk | contribs) (Added A Bank)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to: navigation, search

Novena FPGA Expansion Pinout

Note: LVDS[number] means Bank 2, LVDS[letter] means Bank 3. All DX2 on bank 3


Side A

Expansion Connector Pin Net Name FPGA Pin
A1 F_DX0 K6
A2 F_DX3 H4
A3 F_DX2 H3
A4 F_DX11 M1
A5 DDC_SDA F2
GND GND GND
A6 F_LVDS_11_P R11
A7 F_LVDS_11_N T11
A8 F_DX1 L7
A9 F_LVDSC_N L1
A10 F_LVDSC_P L2
A11 GND GND
A12 F_DX17 G1
A13 GND GND
A14 F_LVDSB_N K5
A15 F_LVDSB_P L5
GND GND GND
A16 F_LVDS15_P U10
A17 F_LVDS15_N V10
A18 GND GND
A19 F_LVDS0_P N5
A20 F_LVDS0_N P6
A21 GND GND
A22 F_LVDS_CK1_P R10
A23 F_LVDS_CK1_N T10
A24 GND GND
A25 F_DX14 T2
GND GND GND
A26 F_LVDS4_P R5
A27 F_LVDS4_N T5
A28 GND GND
A29 F_LVDS1_P T4
A30 F_LVDS1_N V4
A31 GND GND
A32 F_LVDS2_N T3
A33 F_LVDS2_P R3
A34 F_LVDSA_P K4
A35 F_LVDSA_N K3
GND GND GND
A36 GND GND
A37 GND GND
A38 GND GND
A39 GND GND
A40 GND GND