Novena Issue Log
Contents
Bringup status by subsystem
| Subsystem | basic status | extended status | notes |
|---|---|---|---|
| PMIC base | OK | voltages nominal, but on high side for CPU (1.35V) -- need PMIC DVFS driver to dial it back | |
| PMIC advanced | needs driver for further testing | ||
| RTC backup battery | |||
| RTC | (extended status should also measure clock drift) | ||
| debug console | OK | OK | |
| SDHC3 (microSD boot) | OK | ||
| SDHC3 power switch | |||
| DDR3 base | OK | functions at 1066 MT/s, 1 GB configured | |
| DDR3 extended | need to test multiple DIMM/mfg configs | ||
| I2C1 (SMB) | OK | can read out DDR3 I2C config using i2cdump | |
| I2C2 | OK | can read out accelerometer, PMIC bits using i2cdump | |
| I2C3 | OK | ||
| reset button | OK | ||
| USB hub 1 | OK | tested with thumb drive, needs performance testing | |
| USB hub 2 | OK | ditto | |
| USB ext1 | OK | ||
| USB ext1 power switch | |||
| USB ext2 | OK | ||
| USB ext2 power switch | |||
| ASIX ethernet | OK | OK | 84,085,191 bytes in 18.53s = 36 Mbps (limited by external fiber uplink speed)
note that MAC address must be generated and assigned (not fixed in hardware ROM) |
| Gbit ethernet | OK | FAIL | Not stable at 1000 Gbit connection, needs debugging. 80+Mbps performance @ 100Mbit connection speed.
note that MAC address must be generated and assigned (not fixed in hardware ROM) |
| SDHC4 | |||
| utility EEPROM | OK | use 16-bit mode for access. eeprom tools need some tweaking, just wrote a couple bytes and declared success. | |
| audio base | |||
| audio power switch | |||
| speakers | |||
| headphone | |||
| analog mic in | |||
| digital mic | |||
| USB keyboard/mouse port | |||
| USB keyboard/mouse power switch | |||
| USB high current (1.5A) charging | |||
| USB OTG | |||
| HDMI | |||
| FPGA | |||
| FPGA apoptosis option | |||
| on-board USB wifi | |||
| wifi power switch | |||
| PCI-express | |||
| PCI-express power switch | |||
| PCI-express embedded USB | |||
| USIM | |||
| USIM power switch | |||
| LCD port | |||
| LCD port USB | |||
| LCD VCC power switch | |||
| LCD backlight power switch | |||
| touchscreen | |||
| user function button | |||
| uart 3 | |||
| uart 4 | |||
| accelerometer | OK | i2cset -y 0 0x1d 0x16 0x01; i2cdump -y -r 6-8 0 0x1d . seems to accelerometate just fine. | |
| SATA | |||
| SATA power switch | |||
| battery interface | |||
| boot option headers | |||
| JTAG | |||
| FPGA SPI memory | |||
| FPGA SPINOR memory | |||
| FPGA ADC | |||
| Rapsberry Pi peripheral header |
Power consumption notes
System at idle with no PM code running and 1GB standard RAM consumes 11.3V, 0.34A (measured at input regulator cap)
Known issues
Hardware
- Inrush current limiting for 3.3V_DELAYED turnon: R38N should be increased to about 30k. Need to verify with experiment turn-on timing margin (i.e. put smaller values in until failure to determine how much margin is available at 30k to ensure consistency across process variation)
- SN001 has 33k -- revised to 10k to match other boards
- SN004 has 10k (CPU did not boot at all with 47k)
- SN003 has 10k (PMIC does not respond to commands post-boot with 47k)
- SN002 has 10k, but has other problems preventing boot
- Fix bug where reset button does not work due to FPGA pulling boot fuses to look at SATA instead of SD card. Resolution is to change HSWAPEN to high, which turns off FPGA pull-ups. ECO applied to all 5 boards.
- 1Gbit PHY reset circuit (per Micrel datasheet) interferes with driver timing. The reset rises too slowly, driver checks MII status immediately and never retries dynamically (does a static read-out of MII data). Fix is to remove the local reset circuit. ECO applied to all 5 boards.
- PCIE_PWRON signal wasn't connected. Oops! In next rev, it will go to GPIO_16, pad R1. For now, it will be hard-wired to powered on.
ECO list
- R38N change to 10k, 1% 0402 (resolve inrush current limit issue)
- R12F to DNP, R13F to 4.7k, 1% 0402 (resolve boot fuse issue with FPGA pull-ups)
- remove C32G, D12G, R20G, D11G; short across D12G with wire jumper or 0805 resistor, 0 ohm (resolve gbit ethernet reset issue)
- remove R11X, tie gate of Q10X to P3.3V_DELAYED (off of pin 2 of Q11X) (resolve PCIE power on issue)
Software
U-boot
- DDR3: need to come up with alternate poke files for different SO-DIMM types
- DDR3: need to figure out how to configure u-boot to recognize greater amounts of DRAM
- MMC: USDHC3 has to have the CD check return 1 at all times.
Linux
- MMC: device tree novena.dts descriptor edited to note that USDHC3 port is non-removable in order to enable boot
- Power: Driver for power currently assumes fixed regulators, an incorrect assumption. This needs to be changed to use the PFUZE PMIC. Currently, no drivers exist in the source tree (based off of the sabrelite). Recommend using Sabre board for smart devices as the base image instead of sabrelite - todo xobs
- USB/Power: PMIC does not turn on the USB VBUS by default, which causes internal root hub to fail. To fix this:
- add i2c2 to device tree (added to novena.dts)
- run this command to turn on the boost regulator:
i2cset 1 0x08 0x66 0x48
- once USB is on, I can verify/see USB drives in both USB ports. See this:
root@novena:~# lsusb Bus 002 Device 002: ID 05e3:0614 Genesys Logic, Inc. Bus 002 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub Bus 002 Device 007: ID 0b95:772b ASIX Electronics Corp. Bus 002 Device 004: ID 05e3:0614 Genesys Logic, Inc. Bus 002 Device 006: ID 058f:6387 Alcor Micro Corp. Transcend JetFlash Flash Drive Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
- ASIX driver module isn't built into current image. Need to figure out how to turn that on.
- Configuring ASIX:
ip link set dev eth1 down ip link set dev eth1 address de:ad:fe:ed:00:01 ip link set dev eth1 up
