Difference between revisions of "Condensed PVT summary page alone"
(Created page with "=Condensed ECO Summary= {| class="wikitable sortable" |- ! scope="col" | DVT ! scope="col" | PVT ! scope="col" | Notes |- | || ECO1 || |- | R20S 49.9, 1% / REC1005N || DNP || Gi...") |
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Latest revision as of 10:58, 15 November 2013
Condensed ECO Summary
| DVT | PVT | Notes |
|---|---|---|
| ECO1 | ||
| R20S 49.9, 1% / REC1005N | DNP | Gigabit ethernet |
| C16S 2200pF, X7R, 50V, 10% / CAPC1005N | DNP | Gigabit ethernet |
| added | 300, 1% / RES1005N | Gigabit ethernet |
| ECO2 | ||
| R57B 100, 1% / REC1005N | DNP | FPGA |
| ECO4 | ||
| Added | R24G 0 ohm / RES1005N | RX clock path (0 inch option) |
| Added | R22G 0 ohm (DNP) | Rx clock path (5 inch option) |
| Added | R23G 0 ohm (DNP) | Rx clock path (5 inch option) |
| Added | R30G 0 ohm (DNP) / RES1005N | TX clock path (0 inch option) |
| Added | R28G 0 ohm | Tx clock path (5 inch option) |
| Added | R29G 0 ohm | Tx clock path (5 inch option) |
| Added | R27G 0 ohm | Tx clock path (5 inch option) |
| Added | R25G 0 ohm (DNP) | Tx clock path (10 inch option) |
| Added | R26G 0 ohm (DNP) | Tx clock path (10 inch option) |
| ECO5 | ||
| SW11B TS-1187A, Chi Fung (DNP) | TL3342F160QG/TR (DNP) | or equiv (see trigger on chibitronics) |
| SW10B TS-1187A, Chi Fung | TL3342F160QG/TR | or equiv |
| SW10S TS-1187A, Chi Fung | TL3342F160QG/TR | or equiv |
| SW11S TS-1187A, Chi Fung | TL3342F160QG/TR | or equiv |
| ECO6 | ||
| Y11B ABS10-32.768KHZ-7-T 7pF CL | ABS06-32.768KHZ-T 12.5pF CL | |
| ECO7 | ||
| Y10U 12.0000 MHz (SaRonix-eCera F9, 30ppm, 8pF) | 12.0000 MHz (NDK NX5032GB-12MHZ-STD-CSK-5, 30ppm, 8pF) | |
| Y11U 12.0000 MHz (SaRonix-eCera F9, 30ppm, 8pF) | 12.0000 MHz (NDK NX5032GB-12MHZ-STD-CSK-5, 30ppm, 8pF) | |
| ECO8 | ||
| C43M 47uF, 6.3V, 20% X5R | 47uF, 6.3V, 20% X5R (CL31A476MQHNNNE) | |
| C44M 47uF, 6.3V, 20% X5R | 47uF, 6.3V, 20% X5R (CL31A476MQHNNNE) | |
| C45M 47uF, 6.3V, 20% X5R | 47uF, 6.3V, 20% X5R (CL31A476MQHNNNE) | |
| C18M 47uF, 6.3V, 20% X5R | 47uF, 6.3V, 20% X5R (CL31A476MQHNNNE) | |
| C52C 47uF, 6.3V, 20% X5R | 47uF, 6.3V, 20% X5R (CL31A476MQHNNNE) | |
| ECO 9 | ||
| U14F MX25L512CMI-12G | MX25L512EMI-10G | |
| ECO 10 | ||
| Added | R28A 0 ohm | KEY_ROW1 now used to control amp power-down |
| Added | R30A 0 ohm (DNP) | backup option in case the above doesn't work |
| Added | R33A 100k, 1% | Pull-down to ensure PA starts in mute state until CPU I/O is initialized |
| ECO 11 | ||
| C22N 22uF, 10V, X5R, 20% (DNP) | 22uF, 10V, X5R, 20% | |
| ECO 12 | ||
| C21X 0.1uF, 6.3V, X5R 0201 | 0 ohm 0201 | |
| C22X 0.1uF, 6.3V, X5R 0201 | 0 ohm 0201 | |
| ECO 14 | ||
| R33L 47k, 1% | 4.7k, 1% | |
| ECO 15 | ||
| U12F MT41J128M16HA-125 | MT41J128M16JT-125K | |
| ECO 16 | ||
| P16D HRS F19SC-8S-0.5SH | HRS FH19SC-8S-0.5SH(05) | note missing H and (05) |
| ECO 17 | ||
| U200 PMPF0100NPEP | MMPF0100NPAEP | |
| ECO 18 | ||
| D11F CDBMT220L-G | CDBMT220L-G or CDBMT240-HF | |
| ECO 19 | ||
| D10A ESD5Z2.5T1 | ESD5Z3.3T1 | |
| D11A ESD5Z2.5T1 | ESD5Z3.3T1 | |
| D12A ESD5Z2.5T1 | ESD5Z3.3T1 | |
| D12D ESD5Z2.5T1 | ESD5Z3.3T1 | |
| D13A ESD5Z2.5T1 | ESD5Z3.3T1 | |
| D13D ESD5Z2.5T1 | ESD5Z3.3T1 | |
| D13N ESD5Z2.5T1 | ESD5Z3.3T1 | |
| D14A ESD5Z2.5T1 | ESD5Z3.3T1 | |
| D14N ESD5Z2.5T1 | ESD5Z3.3T1 | |
| D15N ESD5Z2.5T1 | ESD5Z3.3T1 | |
| D16N ESD5Z2.5T1 | ESD5Z3.3T1 | |
| ECO 20 | ||
| Added | D17N ESD5Z3.3T1 | protect SMB_SDA |
| R21N 47k, 1% | 330, 1% | repurpose for SMB_SCL use |
| Added | J11L testpoint (DNP) | BATT_REFLASH_ALRT moved to test point |
| ECO 22 | ||
| Added | C35U 4.7uF, 10V, X5R, 10% | |
| Added | R43U 0 ohm |
