Difference between revisions of "Novena FPGA Expansion"

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(Added A Bank)
 
(Added B Bank)
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== Novena FPGA Expansion Pinout ==
 
== Novena FPGA Expansion Pinout ==
 
Note: LVDS[number] means Bank 2, LVDS[letter] means Bank 3. All DX2 on bank 3
 
Note: LVDS[number] means Bank 2, LVDS[letter] means Bank 3. All DX2 on bank 3
−
 
  
 
=== Side A ===
 
=== Side A ===
Line 184: Line 183:
 
|GND
 
|GND
 
|GND
 
|GND
 +
|-
 +
|}
 +
 +
=== Side B ===
 +
{| class="wikitable"
 +
! Expansion Connector Pin
 +
! Net Name
 +
! FPGA Pin
 +
|-
 +
|B1
 +
|F_DX5
 +
|J3
 +
|-
 +
|B2
 +
|F_DX4
 +
|J1
 +
|-
 +
|B3
 +
|DDC_SCL
 +
|J6
 +
|-
 +
|B4
 +
|F_LVDS14_P
 +
|U16
 +
|-
 +
|B5
 +
|F_LVDS14_N
 +
|V16
 +
|-
 +
|GND
 +
|GND
 +
|GND
 +
|-
 +
|B6
 +
|F_DX8
 +
|K2
 +
|-
 +
|B7
 +
|GND
 +
|GND
 +
|-
 +
|B8
 +
|F_LVDS13_P
 +
|T14
 +
|-
 +
|B9
 +
|F_LVDS13_N
 +
|V14
 +
|-
 +
|B10
 +
|F_DX16
 +
|L6
 +
|-
 +
|B11
 +
|F_LVDS12_P
 +
|U13
 +
|-
 +
|B12
 +
|F_LVDS12_N
 +
|V13
 +
|-
 +
|B13
 +
|GND
 +
|GND
 +
|-
 +
|B14
 +
|F_LVDS10_P
 +
|U11
 +
|-
 +
|B15
 +
|F_LVDS10_N
 +
|V11
 +
|-
 +
|GND
 +
|GND
 +
|GND
 +
|-
 +
|B16
 +
|F_DX18
 +
|H7
 +
|-
 +
|B17
 +
|GND
 +
|GND
 +
|-
 +
|B18
 +
|F_LVDS_CK0_P
 +
|R8
 +
|-
 +
|B19
 +
|F_LVDS_CK0_N
 +
|T8
 +
|-
 +
|B20
 +
|GND
 +
|GND
 +
|-
 +
|B21
 +
|F_LVDS9_P
 +
|T9
 +
|-
 +
|B22
 +
|F_LVDS9_N
 +
|V9
 +
|-
 +
|B23
 +
|GND
 +
|GND
 +
|-
 +
|B24
 +
|F_LVDS8_P
 +
|U8
 +
|-
 +
|B25
 +
|F_LVDS8_N
 +
|V8
 +
|-
 +
|GND
 +
|GND
 +
|GND
 +
|-
 +
|B26
 +
|F_LVDS5_P
 +
|R7
 +
|-
 +
|B27
 +
|F_LVDS5_N
 +
|T7
 +
|-
 +
|B28
 +
|F_LVDS6_N
 +
|V6
 +
|-
 +
|B29
 +
|F_LVDS6_P
 +
|T6
 +
|-
 +
|B30
 +
|GND
 +
|GND
 +
|-
 +
|B31
 +
|F_LVDS3_N
 +
|V5
 +
|-
 +
|B32
 +
|F_LVDS3_P
 +
|U5
 +
|-
 +
|B33
 +
|GND
 +
|GND
 +
|-
 +
|B34
 +
|F_LVDS7_P
 +
|U7
 +
|-
 +
|B35
 +
|F_LVDS7_N
 +
|V7
 +
|-
 +
|GND
 +
|GND
 +
|GND
 +
|-
 +
|B36
 +
|F_DX15
 +
|M5
 +
|-
 +
|B37
 +
|F_DX7
 +
|L4
 +
|-
 +
|B38
 +
|F_DX12
 +
|M3
 +
|-
 +
|B39
 +
|F_DX6
 +
|L3
 +
|-
 +
|B40
 +
|F_DX13
 +
|P2
 
|-
 
|-
 
|}
 
|}

Revision as of 05:20, 7 August 2014

Novena FPGA Expansion Pinout

Note: LVDS[number] means Bank 2, LVDS[letter] means Bank 3. All DX2 on bank 3

Side A

Expansion Connector Pin Net Name FPGA Pin
A1 F_DX0 K6
A2 F_DX3 H4
A3 F_DX2 H3
A4 F_DX11 M1
A5 DDC_SDA F2
GND GND GND
A6 F_LVDS_11_P R11
A7 F_LVDS_11_N T11
A8 F_DX1 L7
A9 F_LVDSC_N L1
A10 F_LVDSC_P L2
A11 GND GND
A12 F_DX17 G1
A13 GND GND
A14 F_LVDSB_N K5
A15 F_LVDSB_P L5
GND GND GND
A16 F_LVDS15_P U10
A17 F_LVDS15_N V10
A18 GND GND
A19 F_LVDS0_P N5
A20 F_LVDS0_N P6
A21 GND GND
A22 F_LVDS_CK1_P R10
A23 F_LVDS_CK1_N T10
A24 GND GND
A25 F_DX14 T2
GND GND GND
A26 F_LVDS4_P R5
A27 F_LVDS4_N T5
A28 GND GND
A29 F_LVDS1_P T4
A30 F_LVDS1_N V4
A31 GND GND
A32 F_LVDS2_N T3
A33 F_LVDS2_P R3
A34 F_LVDSA_P K4
A35 F_LVDSA_N K3
GND GND GND
A36 GND GND
A37 GND GND
A38 GND GND
A39 GND GND
A40 GND GND

Side B

Expansion Connector Pin Net Name FPGA Pin
B1 F_DX5 J3
B2 F_DX4 J1
B3 DDC_SCL J6
B4 F_LVDS14_P U16
B5 F_LVDS14_N V16
GND GND GND
B6 F_DX8 K2
B7 GND GND
B8 F_LVDS13_P T14
B9 F_LVDS13_N V14
B10 F_DX16 L6
B11 F_LVDS12_P U13
B12 F_LVDS12_N V13
B13 GND GND
B14 F_LVDS10_P U11
B15 F_LVDS10_N V11
GND GND GND
B16 F_DX18 H7
B17 GND GND
B18 F_LVDS_CK0_P R8
B19 F_LVDS_CK0_N T8
B20 GND GND
B21 F_LVDS9_P T9
B22 F_LVDS9_N V9
B23 GND GND
B24 F_LVDS8_P U8
B25 F_LVDS8_N V8
GND GND GND
B26 F_LVDS5_P R7
B27 F_LVDS5_N T7
B28 F_LVDS6_N V6
B29 F_LVDS6_P T6
B30 GND GND
B31 F_LVDS3_N V5
B32 F_LVDS3_P U5
B33 GND GND
B34 F_LVDS7_P U7
B35 F_LVDS7_N V7
GND GND GND
B36 F_DX15 M5
B37 F_DX7 L4
B38 F_DX12 M3
B39 F_DX6 L3
B40 F_DX13 P2
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