Difference between revisions of "Novena AFE"
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*R17P is wrong. The current value of 45k sets the output to 3.3V. Should be 52.3k to set the output to 3.7V | *R17P is wrong. The current value of 45k sets the output to 3.3V. Should be 52.3k to set the output to 3.7V | ||
*R21C, R20C is too weak. Set to 1k to overcome the internal bias on SP0,1 | *R21C, R20C is too weak. Set to 1k to overcome the internal bias on SP0,1 | ||
| − | + | ===Loop filter tuning (all variants)=== | |
| − | |||
| − | |||
| − | ===Loop filter tuning=== | ||
Generated using ADIsimCLK - save file ad9520-3-calck.clk | Generated using ADIsimCLK - save file ad9520-3-calck.clk | ||
*C38C 1500pF -> 82pF | *C38C 1500pF -> 82pF | ||
| Line 38: | Line 35: | ||
==DAC-specific== | ==DAC-specific== | ||
U14A footprint is flipped. Must rework before power-up. | U14A footprint is flipped. Must rework before power-up. | ||
| + | |||
| + | ==High speed ADC-specific== | ||
| + | *Capacitive loading of VCMO is too large for 0-ohm stability with buffers. Replace R10I, R11I with 620 ohm, 1% resistors. Some tuning could be used later on, e.g. values were chosen conservatively large for stability, but if ripple appears on the line consider reducing resistor to improve ripple performance. | ||
| + | |||
| + | *LVDSC maps to an ineligible bank for high speed clock distribution with DDR input. Lift pins for DI3+/DI3- and wire using the shortest possible wires to the OR+/OR- pins (LVDS6). Cut the traces going to OR+/OR- on the chip, as this function is not used. FPGA code as writ expects this configuration. | ||
| + | |||
| + | ===Probes=== | ||
| + | *Digital probe: for second probe, different I2C addresses are required for the offset and trigger DAC, as well as the I2C-SPI connector. | ||
| + | ** For the I2C-SPI connector, program in a different soft address of 0x54/0x2A (ch2) vs. 0x50/0x28 (ch1) (addresses given in format of 8bit/7bit, where 7bit is the format expected by linux) | ||
| + | ** For trim DAC (U12A), lift pin 1, causing it to float. This gives it an address of 0x98/0x4C (ch2) vs. 0x9C/0x4E (ch1) | ||
| + | ** For trigger DAC (U13A), lift pin 2, causing it to float. This gives it an address of 0x1A/0x0D (ch2) vs. 0x9A/0x4D (ch1) | ||
| + | |||
| + | ==Precision ADC-specific== | ||
| + | * Cut & jumper LVDS_C to LVDS_4 to get around DDR banking restriction vs. PLL clock source in FPGA. Rework is done by routing wires from vias on the bottom side of the board, contacting the LVDS_C vias and wiring to LVDS_4 pins near the +5V pin connector. Then, the trace to the connector from the LVDS_C via is cut to avoid the hanging stub. | ||
| + | |||
| + | =Firmware= | ||
| + | ==libnl== | ||
| + | libnl in debian wheezy is too old. | ||
| + | |||
| + | Please fetch the archive | ||
| + | |||
| + | http://bunniefoo.com/novena/libnl-novena.tar | ||
| + | |||
| + | And install the .deb files contained within. | ||
Latest revision as of 14:31, 20 April 2014
Notes on Novena AFE
Contents
EVT bringup notes
All variants
- R17P is wrong. The current value of 45k sets the output to 3.3V. Should be 52.3k to set the output to 3.7V
- R21C, R20C is too weak. Set to 1k to overcome the internal bias on SP0,1
Loop filter tuning (all variants)
Generated using ADIsimCLK - save file ad9520-3-calck.clk
- C38C 1500pF -> 82pF
- R23C 3k -> 2.7k
- C37C 4.7uF -> 3.3nF
- R25C 2.1k -> 1.3k
- C36C 2200pF -> 270pF
- Loop bandwidth: 102 kHz
- Phase margin: 43.6 deg
- Zero: 37.1 kHz
- Pole: 275 kHz
- Last pole: 951kHz
Estimated phase noise and jitter to ADC:
Frequency: 1.00000GHz
Broadband Jitter (>1kHz) = 558fs rms
SNR = 69.10dB ENOB = 11.52bits
at IF Freq = 100MHz
Integrated Phase Noise from 100kHz to 1.25MHz
Timing Jitter = 302fs rms
Phase Jitter EVM = 0.19 %rms
Phase Jitter = 0.109 degrees rms
ACI / ACR = -57.5dBc
Delay from Ref to OUT3 is 250ps
DAC-specific
U14A footprint is flipped. Must rework before power-up.
High speed ADC-specific
- Capacitive loading of VCMO is too large for 0-ohm stability with buffers. Replace R10I, R11I with 620 ohm, 1% resistors. Some tuning could be used later on, e.g. values were chosen conservatively large for stability, but if ripple appears on the line consider reducing resistor to improve ripple performance.
- LVDSC maps to an ineligible bank for high speed clock distribution with DDR input. Lift pins for DI3+/DI3- and wire using the shortest possible wires to the OR+/OR- pins (LVDS6). Cut the traces going to OR+/OR- on the chip, as this function is not used. FPGA code as writ expects this configuration.
Probes
- Digital probe: for second probe, different I2C addresses are required for the offset and trigger DAC, as well as the I2C-SPI connector.
- For the I2C-SPI connector, program in a different soft address of 0x54/0x2A (ch2) vs. 0x50/0x28 (ch1) (addresses given in format of 8bit/7bit, where 7bit is the format expected by linux)
- For trim DAC (U12A), lift pin 1, causing it to float. This gives it an address of 0x98/0x4C (ch2) vs. 0x9C/0x4E (ch1)
- For trigger DAC (U13A), lift pin 2, causing it to float. This gives it an address of 0x1A/0x0D (ch2) vs. 0x9A/0x4D (ch1)
Precision ADC-specific
- Cut & jumper LVDS_C to LVDS_4 to get around DDR banking restriction vs. PLL clock source in FPGA. Rework is done by routing wires from vias on the bottom side of the board, contacting the LVDS_C vias and wiring to LVDS_4 pins near the +5V pin connector. Then, the trace to the connector from the LVDS_C via is cut to avoid the hanging stub.
Firmware
libnl
libnl in debian wheezy is too old.
Please fetch the archive
http://bunniefoo.com/novena/libnl-novena.tar
And install the .deb files contained within.
