Difference between revisions of "Novena ddr3 notes"

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(→‎1-rank calibrations)
(→‎SPD values)
 
(6 intermediate revisions by the same user not shown)
Line 206: Line 206:
 
MPDGHWST2 PHY1 (0x021b4884) = 0x03390001
 
MPDGHWST2 PHY1 (0x021b4884) = 0x03390001
 
MPDGHWST3 PHY1 (0x021b4888) = 0x035F0001
 
MPDGHWST3 PHY1 (0x021b4888) = 0x035F0001
 +
</pre>
 +
 +
SN001 Kingston 2-rank KVR16S11/4 cal, with new uboot (1/13):
 +
<pre>
 +
write starting at 10000000
 +
checksum: 7ffd001e
 +
read starting at 10000000
 +
computed: 7ffd001e, readback: 7fe961b9
 +
Start write leveling calibration
 +
.Write leveling calibration completed, errcount: 0
 +
MMDC_MPWLDECTRL0 after write level cal: 0x002A002E
 +
MMDC_MPWLDECTRL1 after write level cal: 0x0015004E
 +
MMDC_MPWLDECTRL0 after write level cal: 0x00640150
 +
MMDC_MPWLDECTRL1 after write level cal: 0x00680126
 +
init cs0: 1 cs1: 1
 +
cal cs0: 1 cs1: 0
 +
db size: 2
 +
Starting DQS gating calibration...
 +
.errorcount: 0
 +
DQS gating calibration completed, hit enter to proceed.
 +
Starting read calibration...
 +
intdel0: 40404040 / intdel1: 40404040
 +
.errorcount: 0
 +
Read calibration completed, hit enter to continue
 +
Starting write calibration...
 +
intdel0: 40404040 / intdel1: 40404040
 +
.errorcount: 0
 +
Write calibration completed, hit enter to continue
 +
MMDC registers updated from calibration
 +
 +
Read DQS Gating calibration
 +
MPDGCTRL0 PHY0 (0x021b083c) = 0x437E041A
 +
MPDGCTRL1 PHY0 (0x021b0840) = 0x03500445
 +
MPDGCTRL0 PHY1 (0x021b483c) = 0x4473053B
 +
MPDGCTRL1 PHY1 (0x021b4840) = 0x050D046A
 +
 +
Read calibration
 +
MPRDDLCTL PHY0 (0x021b0848) = 0x45414642
 +
MPRDDLCTL PHY1 (0x021b4848) = 0x4548424C
 +
 +
Write calibration
 +
MPWRDLCTL PHY0 (0x021b0850) = 0x45414545
 +
MPWRDLCTL PHY1 (0x021b4850) = 0x45324641
 +
 +
Status registers, upper and lower bounds, for read DQS gating.
 +
MPDGHWST0 PHY0 (0x021b087c) = 0x02DA0001
 +
MPDGHWST1 PHY0 (0x021b0880) = 0x02BE0001
 +
MPDGHWST2 PHY0 (0x021b0884) = 0x03050001
 +
MPDGHWST3 PHY0 (0x021b0888) = 0x02900001
 +
MPDGHWST0 PHY1 (0x021b487c) = 0x037B0001
 +
MPDGHWST1 PHY1 (0x021b4880) = 0x03330001
 +
MPDGHWST2 PHY1 (0x021b4884) = 0x032A0001
 +
MPDGHWST3 PHY1 (0x021b4888) = 0x034D0001
 +
errorcount: 0
 +
init cs0: 1 cs1: 1
 +
cal cs0: 1 cs1: 0
 +
db size: 2
 +
Starting DQS gating calibration...
 +
.errorcount: 0
 +
DQS gating calibration completed, hit enter to proceed.
 +
Starting read calibration...
 +
intdel0: 40404040 / intdel1: 40404040
 +
.errorcount: 0
 +
Read calibration completed, hit enter to continue
 +
Starting write calibration...
 +
intdel0: 40404040 / intdel1: 40404040
 +
.errorcount: 0
 +
Write calibration completed, hit enter to continue
 +
MMDC registers updated from calibration
 +
 +
Read DQS Gating calibration
 +
MPDGCTRL0 PHY0 (0x021b083c) = 0x4401041B
 +
MPDGCTRL1 PHY0 (0x021b0840) = 0x03530443
 +
MPDGCTRL0 PHY1 (0x021b483c) = 0x4475053F
 +
MPDGCTRL1 PHY1 (0x021b4840) = 0x050E046A
 +
 +
Read calibration
 +
MPRDDLCTL PHY0 (0x021b0848) = 0x45424642
 +
MPRDDLCTL PHY1 (0x021b4848) = 0x4548424C
 +
 +
Write calibration
 +
MPWRDLCTL PHY0 (0x021b0850) = 0x45414545
 +
MPWRDLCTL PHY1 (0x021b4850) = 0x45324641
 +
 +
Status registers, upper and lower bounds, for read DQS gating.
 +
MPDGHWST0 PHY0 (0x021b087c) = 0x02DB0001
 +
MPDGHWST1 PHY0 (0x021b0880) = 0x02C10001
 +
MPDGHWST2 PHY0 (0x021b0884) = 0x03030001
 +
MPDGHWST3 PHY0 (0x021b0888) = 0x02930001
 +
MPDGHWST0 PHY1 (0x021b487c) = 0x037F0001
 +
MPDGHWST1 PHY1 (0x021b4880) = 0x03350001
 +
MPDGHWST2 PHY1 (0x021b4884) = 0x032A0001
 +
MPDGHWST3 PHY1 (0x021b4888) = 0x034E0001
 +
errorcount: 0
 +
write starting at 10000000
 +
checksum: 7ffd001e
 +
read starting at 10000000
 +
computed: 7ffd001e, readback: 7ffd001e
 +
### main_loop entered: bootdelay=1
 
</pre>
 
</pre>
  
Line 251: Line 350:
 
errorcount: 0
 
errorcount: 0
 
</pre>
 
</pre>
 +
 +
With new codebase integrated into u-boot (jan 13):
 +
<pre>
 +
MMDC_MPWLDECTRL0 after write level cal: 0x003F0046
 +
MMDC_MPWLDECTRL1 after write level cal: 0x00660059
 +
MMDC_MPWLDECTRL0 after write level cal: 0x005F0107
 +
MMDC_MPWLDECTRL1 after write level cal: 0x00640115
 +
 +
Read DQS Gating calibration
 +
MPDGCTRL0 PHY0 (0x021b083c) = 0x436D037D
 +
MPDGCTRL1 PHY0 (0x021b0840) = 0x037F040D
 +
MPDGCTRL0 PHY1 (0x021b483c) = 0x44500447
 +
MPDGCTRL1 PHY1 (0x021b4840) = 0x04570421
 +
 +
Read calibration
 +
MPRDDLCTL PHY0 (0x021b0848) = 0x48454244
 +
MPRDDLCTL PHY1 (0x021b4848) = 0x474C434F
 +
 +
Write calibration
 +
MPWRDLCTL PHY0 (0x021b0850) = 0x32304137
 +
MPWRDLCTL PHY1 (0x021b4850) = 0x452C4637
 +
 +
Status registers, upper and lower bounds, for read DQS gating.
 +
MPDGHWST0 PHY0 (0x021b087c) = 0x02BD0001
 +
MPDGHWST1 PHY0 (0x021b0880) = 0x02AD0001
 +
MPDGHWST2 PHY0 (0x021b0884) = 0x02CD0001
 +
MPDGHWST3 PHY0 (0x021b0888) = 0x02BF0001
 +
MPDGHWST0 PHY1 (0x021b487c) = 0x03070001
 +
MPDGHWST1 PHY1 (0x021b4880) = 0x03100001
 +
MPDGHWST2 PHY1 (0x021b4884) = 0x02E10001
 +
MPDGHWST3 PHY1 (0x021b4888) = 0x03170001
 +
</pre>
 +
Errcount is zero, and the trivial write/read test seems to work with these parameters.
  
 
Note above that the errorcount is 0 on this run.
 
Note above that the errorcount is 0 on this run.
Line 304: Line 436:
 
Board layout files for SO-DIMMs. Looks like 90% of all SO-DIMMs use the reference design with very, very minor tweaks. There are basically two types of SO-DIMM layouts, one for single-rank, and one for dual-rank. The exception is Samsung, their low power DDR line has a novel layout.  
 
Board layout files for SO-DIMMs. Looks like 90% of all SO-DIMMs use the reference design with very, very minor tweaks. There are basically two types of SO-DIMM layouts, one for single-rank, and one for dual-rank. The exception is Samsung, their low power DDR line has a novel layout.  
 
http://www.jedec.org/standards-documents/focus/memory-module-designs-dimms/DDR3/204-pin%20Unbuffered%20SODIMMs
 
http://www.jedec.org/standards-documents/focus/memory-module-designs-dimms/DDR3/204-pin%20Unbuffered%20SODIMMs
 +
 +
==SPD values==
 +
 +
===Kingston HP594907===
 +
1-rank 1GByte, calibration OK
 +
<pre>
 +
0000: 92 10 0b 03 02 11 00 01 03 52 01 08 0c 00 3e 00    .........R....>.
 +
0010: 69 78 69 30 69 11 20 89 70 03 3c 3c 00 f0 83 81    ixi0i. .p.<<....
 +
0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 21 00    ..............!.
 +
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0070: 00 00 00 00 00 01 98 06 11 17 81 3a 84 08 1a c6    ...........:....
 +
0080: 48 50 35 39 34 39 30 37 2d 48 52 31 2d 45 4c 46    HP594907-HR1-ELF
 +
0090: 45 55 00 00 00 00 00 00 00 00 00 00 00 00 00 00    EU..............
 +
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5a    ...............Z
 +
00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
</pre>
 +
 +
===Crucial CT51264BC1067.M16FKD===
 +
2-rank 4Gbyte, calibration NG
 +
<pre>
 +
0000: 92 10 0b 03 03 19 00 09 03 52 01 08 0f 00 1e 00    .........R......
 +
0010: 69 78 69 3c 69 11 2c 95 00 05 3c 3c 01 2c 82 05    ixi<i.,...<<.,..
 +
0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 05 00    ................
 +
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0070: 00 00 00 00 00 85 9b 00 0c 2f 00 00 00 00 41 e1    ........./....A.
 +
0080: 43 54 35 31 32 36 34 42 43 31 30 36 37 2e 4d 31    CT51264BC1067.M1
 +
0090: 36 46 4b 44 80 2c 00 00 00 00 00 00 00 00 00 00    6FKD.,..........
 +
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
00c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
00d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
00e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
00f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
</pre>
 +
 +
===Crucial CT25664BC1067.M8FMR====
 +
1-rank 2GB, calibration NG
 +
<pre>
 +
0000: 92 10 0b 03 03 19 00 01 03 52 01 08 0f 00 1e 00    .........R......
 +
0010: 69 78 69 3c 69 11 2c 95 00 05 3c 3c 01 2c 82 05    ixi<i.,...<<.,..
 +
0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 01 00    ................
 +
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0070: 00 00 00 00 00 85 9b 00 0c 2f 00 00 00 00 4e 59    ........./....NY
 +
0080: 43 54 32 35 36 36 34 42 43 31 30 36 37 2e 4d 38    CT25664BC1067.M8
 +
0090: 46 4d 52 00 80 2c 00 00 00 00 00 00 00 00 00 00    FMR..,..........
 +
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
00c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
00d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
00e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
00f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
</pre>
 +
 +
===Corsair CM3X4GSD1066===
 +
2-rank 4GB, calibration NG
 +
<pre>
 +
0000: 92 10 0b 03 03 19 00 09 03 52 01 08 0f 00 1c 00    .........R......
 +
0010: 69 78 69 3c 69 11 2c 95 00 05 3c 3c 01 2c 83 0c    ixi<i.,...<<.,..
 +
0020: 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0030: 00 00 00 00 00 00 00 00 00 00 00 00 10 11 03 00    ................
 +
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0070: 00 00 00 00 00 02 9e 01 00 00 00 00 00 00 5b 4a    ..............[J
 +
0080: 43 4d 33 58 34 47 53 44 31 30 36 36 20 20 20 20    CM3X4GSD1066   
 +
0090: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00      ..............
 +
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
</pre>
 +
 +
===PNY Generic 4GB===
 +
2-rank 4GB, calibration NG. No brand or model number.
 +
<pre>
 +
0000: 92 10 0b 03 03 19 00 09 03 52 01 08 0f 00 1e 00    .........R......
 +
0010: 69 78 69 3c 69 11 2c 95 00 05 3c 3c 01 2c 82 05    ixi<i.,...<<.,..
 +
0020: 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 05 00    ................
 +
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0070: 00 00 00 00 00 01 ba 00 00 00 00 00 00 00 07 06    ................
 +
0080: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20                   
 +
0090: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00      ..............
 +
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
</pre>
 +
 +
===Samsung M473B5273DH0-YK0===
 +
2-rank 4GB, custom layout. Calibration NG.
 +
<pre>
 +
0000: 92 11 0b 03 03 19 02 09 03 11 01 08 0a 00 fe 00    ................
 +
0010: 69 78 69 30 69 11 18 81 00 05 3c 3c 00 f0 83 01    ixi0i.....<<....
 +
0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0030: 00 00 00 00 00 00 00 00 00 00 00 00 0b 11 65 00    ..............e.
 +
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0070: 00 00 00 00 00 80 ce 01 12 09 22 38 5d 69 32 fb    .........."8]i2.
 +
0080: 4d 34 37 33 42 35 32 37 33 44 48 30 2d 59 4b 30    M473B5273DH0-YK0
 +
0090: 20 20 00 00 80 ce 00 00 00 57 30 59 41 30 30 30      .......W0YA000
 +
00a0: 01 00 01 00 00 00 00 00 00 00 00 00 00 00 00 01    ................
 +
00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 30 37 00    .............07.
 +
00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
</pre>
 +
 +
===Centon 2GB MICU58PIA===
 +
2-rank 2GB, calibration OK.
 +
<pre>
 +
0000: 92 01 0b 03 02 11 00 09 03 52 01 08 0f 00 1c 00    .........R......
 +
0010: 69 78 69 3c 69 11 2c 95 70 03 3c 3c 01 2c 03 0d    ixi<i.,.p.<<.,..
 +
0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 05 00    ................
 +
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0070: 00 00 00 00 00 83 19 00 00 00 00 00 00 00 01 87    ................
 +
0080: 4d 49 43 55 35 38 50 49 41 20 20 20 20 20 20 20    MICU58PIA     
 +
0090: 20 20 00 00 00 00 43 45 4e 54 4f 4e 20 32 47 42      ....CENTON 2GB
 +
00a0: 20 44 44 52 33 20 53 4f 44 49 4d 4d 20 20 20 20    DDR3 SODIMM   
 +
00b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
00c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
00d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
00e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
00f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
</pre>
 +
 +
===Kingston 99U5428-055===
 +
2-rank 4GB, calibration OK
 +
<pre>
 +
0000: 92 11 0b 03 03 19 00 09 03 52 01 08 0a 00 fe 00    .........R......
 +
0010: 69 78 69 30 69 11 18 81 00 05 3c 3c 00 f0 83 81    ixi0i.....<<....
 +
0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 65 00    ..............e.
 +
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0070: 00 00 00 00 00 01 98 04 12 45 36 13 da 38 71 7b    .........E6..8q{
 +
0080: 39 39 55 35 34 32 38 2d 30 35 35 2e 41 30 30 47    99U5428-055.A00G
 +
0090: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00      ..............
 +
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5a    ...............Z
 +
</pre>
 +
 +
==Sample boot log==
 +
<pre>
 +
U-Boot 2012.10-rc1-00045-g7c35808-dirty (Feb 07 2013 - 04:10:45)
 +
 +
U-Boot code: 009073E0 -> 18000000  BSS: -> 180326C0
 +
CPU:  Freescale i.MX6Q rev1.2 at 792 MHz
 +
Reset cause: POR
 +
Board: Novena Quattuor
 +
 +
SPD dump:
 +
0000: 92 10 0b 03 03 19 00 09 03 52 01 08 0f 00 1e 00    .........R......
 +
0010: 69 78 69 3c 69 11 2c 95 00 05 3c 3c 01 2c 82 05    ixi<i.,...<<.,..
 +
0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 05 00    ................
 +
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
0070: 00 00 00 00 00 85 9b 00 0c 2f 00 00 00 00 41 e1    ........./....A.
 +
0080: 43 54 35 31 32 36 34 42 43 31 30 36 37 2e 4d 31    CT51264BC1067.M1
 +
0090: 36 46 4b 44 80 2c 00 00 00 00 00 00 00 00 00 00    6FKD.,..........
 +
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
 +
00b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
00c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
00d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
00e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
00f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 +
 +
Raw DDR3 characteristics based on SPD:
 +
  8 banks
 +
  Individual chip density is 2048 Mib
 +
  Rows: 15, Cols: 10
 +
  Supports 1.5V operation.
 +
  Module has 2 rank(s)
 +
  Chips have a width of 8 bits
 +
  Module width is 64 bits, no ECC
 +
  Module capacity is 4 GiB
 +
  DDR3-1066 speed rating detected
 +
Derived optimal timing parameters, in 533MHz cycles:
 +
  CAS latency: 7
 +
  tWRmin: 8
 +
  tRCDmin: 7
 +
  tRRDmin: 4
 +
  tRPmin: 7
 +
  tRAS: 20
 +
  tRC: 27
 +
  tRFCmin: 86
 +
  tWTRmin: 4
 +
  tRTPmin: 4
 +
  tFAW: 20
 +
Info: no thermal sensor on-module
 +
Vendor ID: 0x9b85
 +
Module name: CT51264BC1067.M16F
 +
 +
Reprogramming DDR timings...
 +
Original CTL: c41a0000
 +
Optimal CTL: c41a0000
 +
Original ASP: 0000003f
 +
Optimal ASP: 0000003f
 +
Original CFG0: babf79a5
 +
Optimal CFG0: 55bf7814
 +
Original CFG1: ff738f66
 +
Optimal CFG1: db538f66
 +
Original CFG2: 01ff00db
 +
Optimal CFG2: 01ff00db
 +
 +
Reference read/write test prior to tuning
 +
write starting at 10000000
 +
checksum: 7ffd001e
 +
read starting at 10000000
 +
computed: 7ffd001e, readback: 683e0a03
 +
 +
Fly-by calibration
 +
Start write leveling calibration
 +
.Write leveling calibration completed, errcount: 0
 +
Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.
 +
MMDC_MPWLDECTRL0 after write level cal: 0x001F001F
 +
MMDC_MPWLDECTRL1 after write level cal: 0x001F001F
 +
MMDC_MPWLDECTRL0 after write level cal: 0x00440044
 +
MMDC_MPWLDECTRL1 after write level cal: 0x00440044
 +
Fly-by calibration seems to have failed. Guessing values for wcal based on rank...
 +
 +
DQS delay calibration
 +
init cs0: 1 cs1: 1
 +
cal cs0: 1 cs1: 0
 +
db size: 2
 +
Starting DQS gating calibration...
 +
.errorcount: 0
 +
DQS gating calibration completed, hit enter to proceed.
 +
Starting read calibration...
 +
intdel0: 40404040 / intdel1: 40404040
 +
.errorcount: 0
 +
Read calibration completed, hit enter to continue
 +
Starting write calibration...
 +
intdel0: 40404040 / intdel1: 40404040
 +
.errorcount: 0
 +
Write calibration completed, hit enter to continue
 +
MMDC registers updated from calibration
 +
 +
Read DQS Gating calibration
 +
MPDGCTRL0 PHY0 (0x021b083c) = 0x46030623
 +
MPDGCTRL1 PHY0 (0x021b0840) = 0x054F0623
 +
MPDGCTRL0 PHY1 (0x021b483c) = 0x4677073B
 +
MPDGCTRL1 PHY1 (0x021b4840) = 0x0704065E
 +
 +
Read calibration
 +
MPRDDLCTL PHY0 (0x021b0848) = 0x463E4447
 +
MPRDDLCTL PHY1 (0x021b4848) = 0x48444049
 +
 +
Write calibration
 +
MPWRDLCTL PHY0 (0x021b0850) = 0x463F4641
 +
MPWRDLCTL PHY1 (0x021b4850) = 0x43364741
 +
 +
Status registers, upper and lower bounds, for read DQS gating.
 +
MPDGHWST0 PHY0 (0x021b087c) = 0x03E30001
 +
MPDGHWST1 PHY0 (0x021b0880) = 0x03C30001
 +
MPDGHWST2 PHY0 (0x021b0884) = 0x03E30001
 +
MPDGHWST3 PHY0 (0x021b0888) = 0x038F0001
 +
MPDGHWST0 PHY1 (0x021b487c) = 0x047B0001
 +
MPDGHWST1 PHY1 (0x021b4880) = 0x04370001
 +
MPDGHWST2 PHY1 (0x021b4884) = 0x041E0001
 +
MPDGHWST3 PHY1 (0x021b4888) = 0x04440001
 +
errorcount: 0
 +
init cs0: 1 cs1: 1
 +
cal cs0: 1 cs1: 0
 +
db size: 2
 +
Starting DQS gating calibration...
 +
.errorcount: 0
 +
DQS gating calibration completed, hit enter to proceed.
 +
Starting read calibration...
 +
intdel0: 40404040 / intdel1: 40404040
 +
.errorcount: 0
 +
Read calibration completed, hit enter to continue
 +
Starting write calibration...
 +
intdel0: 40404040 / intdel1: 40404040
 +
.errorcount: 0
 +
Write calibration completed, hit enter to continue
 +
MMDC registers updated from calibration
 +
 +
Read DQS Gating calibration
 +
MPDGCTRL0 PHY0 (0x021b083c) = 0x46030623
 +
MPDGCTRL1 PHY0 (0x021b0840) = 0x05500623
 +
MPDGCTRL0 PHY1 (0x021b483c) = 0x4677073A
 +
MPDGCTRL1 PHY1 (0x021b4840) = 0x0704065E
 +
 +
Read calibration
 +
MPRDDLCTL PHY0 (0x021b0848) = 0x463E4447
 +
MPRDDLCTL PHY1 (0x021b4848) = 0x4844404A
 +
 +
Write calibration
 +
MPWRDLCTL PHY0 (0x021b0850) = 0x463F4641
 +
MPWRDLCTL PHY1 (0x021b4850) = 0x43374741
 +
 +
Status registers, upper and lower bounds, for read DQS gating.
 +
MPDGHWST0 PHY0 (0x021b087c) = 0x03E30001
 +
MPDGHWST1 PHY0 (0x021b0880) = 0x03C30001
 +
MPDGHWST2 PHY0 (0x021b0884) = 0x03E30001
 +
MPDGHWST3 PHY0 (0x021b0888) = 0x03900001
 +
MPDGHWST0 PHY1 (0x021b487c) = 0x047A0001
 +
MPDGHWST1 PHY1 (0x021b4880) = 0x04370001
 +
MPDGHWST2 PHY1 (0x021b4884) = 0x041E0001
 +
MPDGHWST3 PHY1 (0x021b4888) = 0x04440001
 +
errorcount: 0
 +
 +
Reference read/write test post-tuning
 +
write starting at 10000000
 +
checksum: 7ffd001e
 +
read starting at 10000000
 +
computed: 7ffd001e, readback: 7ffd001e
 +
ddrSPD.capacity: 00008000
 +
Ramsize according to SPD: f0000000
 +
Set gd->ram_size to f0000000
 +
monitor len: 1772B2E0
 +
ramsize: F0000000
 +
TLB table at: ffff0000
 +
Top of RAM usable for U-Boot at: ffff0000
 +
Reserving 10248k for malloc() at: ff5ee000
 +
Reserving 32 Bytes for Board Info at: ff5edfe0
 +
Reserving 136 Bytes for Global Data at: ff5edf58
 +
New Stack Pointer is: ff5edf48
 +
RAM Configuration:
 +
Bank #0: 10000000 3.8 GiB
 +
relocation Offset is: 00000000
 +
_TEXT_BASE: 009073e0
 +
addr_sp: ff5edf48
 +
monitor flash len: 0002E0C8
 +
Now running in RAM - U-Boot at: 009073e0
 +
MMC:  FSL_SDHC: 0, FSL_SDHC: 1
 +
board_mmc_getcd(): esdhc_base 0x02198000
 +
*** Warning - bad CRC, using default environment
 +
 +
In:    serial
 +
Out:  serial
 +
Err:  serial
 +
Hit any key to stop autoboot:  0
 +
board_mmc_getcd(): esdhc_base 0x02198000
 +
mmc0 is current device
 +
board_mmc_getcd(): esdhc_base 0x02198000
 +
board_mmc_getcd(): esdhc_base 0x02198000
 +
reading boot.scr
 +
 +
188 bytes read
 +
Running bootscript from mmc ...
 +
## Executing script at 10800000
 +
board_mmc_getcd(): esdhc_base 0x02198000
 +
reading uImage-novena.bin
 +
 +
3887512 bytes read
 +
board_mmc_getcd(): esdhc_base 0x02198000
 +
reading uImage-novena.dtb
 +
 +
17840 bytes read
 +
## Booting kernel from Legacy Image at 12000000 ...
 +
  Image Name:  Angstrom/3.6.0+r8+git/novena
 +
  Image Type:  ARM Linux Kernel Image (uncompressed)
 +
  Data Size:    3887448 Bytes = 3.7 MiB
 +
  Load Address: 10008000
 +
  Entry Point:  10008000
 +
  Verifying Checksum ... OK
 +
## Flattened Device Tree blob at 11ff0000
 +
  Booting using the fdt blob at 0x11ff0000
 +
  Loading Kernel Image ... OK
 +
OK
 +
  Using Device Tree in place at 11ff0000, end 11ff75af
 +
 +
Starting kernel ...
 +
</pre>

Latest revision as of 14:03, 7 February 2013

Software support

In order to tune DDR3, a RAM-only version of u-boot was created. This u-boot is totally stripped down to basically an interactive shell with few features. A set of calibration access routines were added: 

tmd     - memory display for tuning
tmdel   - delay calibration
tmrr    - read data and checksum from write
tmtest  - simple RAM read/write test
tmw     - memory write (fill) for tuning
tmw2    - memory write (fill) for tuning, ignores trailing data
tmwcal  - write calibration
tmww    - write random data to RAM

Routines like tmrr and tmww just generate traffic to trigger the scope.

tmwcal and tmdel perform the DDR3 calibration routines, per Freescale application notes.

Currently, all the other shell routines break because global/static variable storage is broken. u-boot really tries hard to relocate itself to a new location in RAM, which I don't need it to do. Right now I just jump out of board init and call the interactive shell directly, skipping the board_init_f function which does the relocation. The only thing I'm really missing is hush functionality (which makes up-arrow work) but in the end I decided it wasn't worth the debugging to get that piece working.

To build this special u-boot, do the following.

Check out the tree: 

git clone git@github.com:sutajiokousagi/u-boot-imx6.git

Set up the environment (as necessary per toolchain, this is for the OE self-built chain): 

source /usr/local/oecore-x86_64/environment-setup-armv7a-angstrom-linux-gnueabi

build it: 

make clean; make novena-ramtune_config; make

This should result in a u-boot.imx that is about 80k in size. It's targeted to load into OCRAM at address 0x009073e0. You can grow the image up to about 160k or so in size and it will still work.

burn it: 

sudo dd if=u-boot.imx of=/dev/sdX seek=2

This locates the u-boot onto the SD card into the location expected by the initial bootstrapping ROM.

Bringup notes

First, it's important to note that it's impossible to write-level calibrate any memory made by Micron. This is because Micron only mirrors the calibration clock to DQ0 of each memory. However, other manufacturers, such as Kingston and Samsung, mirror the clock to all lanes, allowing for such calibration.

That being said, it was possible to collect calibration runs from several devices.

2-rank calibrations

SN001 samsung M473B5273DH0-YK0 cal (note custom layout to Samsung): 

Write leveling calibration completed, errcount: 0
MMDC_MPWLDECTRL0 after write level cal: 0x000C0009
MMDC_MPWLDECTRL1 after write level cal: 0x003A002B
MMDC_MPWLDECTRL0 after write level cal: 0x00460052
MMDC_MPWLDECTRL1 after write level cal: 0x004D0101
Novena U-Boot > tmwcal
Start write leveling calibration 
.
Write leveling calibration completed, errcount: 0
MMDC_MPWLDECTRL0 after write level cal: 0x000C000A
MMDC_MPWLDECTRL1 after write level cal: 0x0039002B
MMDC_MPWLDECTRL0 after write level cal: 0x00460052
MMDC_MPWLDECTRL1 after write level cal: 0x004D0072
Novena U-Boot > 

Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x4418040F
MPDGCTRL1 PHY0 (0x021b0840) = 0x040F0457
MPDGCTRL0 PHY1 (0x021b483c) = 0x45001440
MPDGCTRL1 PHY1 (0x021b4840) = 0x0E000440

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x40404040
MPRDDLCTL PHY1 (0x021b4848) = 0x40404040

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x2D2E432F
MPWRDLCTL PHY1 (0x021b4850) = 0x4736483E

Status registers, upper and lower bounds, for read DQS gating. 
MPDGHWST0 PHY0 (0x021b087c) = 0x02CF0001
MPDGHWST1 PHY0 (0x021b0880) = 0x02D80001
MPDGHWST2 PHY0 (0x021b0884) = 0x03170001
MPDGHWST3 PHY0 (0x021b0888) = 0x02CF0001
MPDGHWST0 PHY1 (0x021b487c) = 0x03000040
MPDGHWST1 PHY1 (0x021b4880) = 0x03400040
MPDGHWST2 PHY1 (0x021b4884) = 0x03000040
MPDGHWST3 PHY1 (0x021b4888) = 0x07C007C0

SN004 Samsung M473B5273DH0-YK0 cal (note custom layout to Samsung): 

Write leveling calibration completed, errcount: 0
MMDC_MPWLDECTRL0 after write level cal: 0x00160014
MMDC_MPWLDECTRL1 after write level cal: 0x003F0037
MMDC_MPWLDECTRL0 after write level cal: 0x004E0057
MMDC_MPWLDECTRL1 after write level cal: 0x01040108

Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x4425041D
MPDGCTRL1 PHY0 (0x021b0840) = 0x04180455
MPDGCTRL0 PHY1 (0x021b483c) = 0x45001440
MPDGCTRL1 PHY1 (0x021b4840) = 0x0E000440

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x40404040
MPRDDLCTL PHY1 (0x021b4848) = 0x40404040

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x2E324134
MPWRDLCTL PHY1 (0x021b4850) = 0x4737493F

Status registers, upper and lower bounds, for read DQS gating. 
MPDGHWST0 PHY0 (0x021b087c) = 0x02DD0001
MPDGHWST1 PHY0 (0x021b0880) = 0x02E50001
MPDGHWST2 PHY0 (0x021b0884) = 0x03150001
MPDGHWST3 PHY0 (0x021b0888) = 0x02D80001
MPDGHWST0 PHY1 (0x021b487c) = 0x03000040
MPDGHWST1 PHY1 (0x021b4880) = 0x03400040
MPDGHWST2 PHY1 (0x021b4884) = 0x03000040
MPDGHWST3 PHY1 (0x021b4888) = 0x07C007C0

Kingston 2-rank KVR16S11/4 cal: 

Write leveling calibration completed, errcount: 0
MMDC_MPWLDECTRL0 after write level cal: 0x000F001B
MMDC_MPWLDECTRL1 after write level cal: 0x017E003B
MMDC_MPWLDECTRL0 after write level cal: 0x00490135
MMDC_MPWLDECTRL1 after write level cal: 0x0061010F
Novena U-Boot > tmwcal
Start write leveling calibration 
.
Write leveling calibration completed, errcount: 0
MMDC_MPWLDECTRL0 after write level cal: 0x000F001A
MMDC_MPWLDECTRL1 after write level cal: 0x017E003B
MMDC_MPWLDECTRL0 after write level cal: 0x00490135
MMDC_MPWLDECTRL1 after write level cal: 0x0062010E

Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x44001440
MPDGCTRL1 PHY0 (0x021b0840) = 0x0E000440
MPDGCTRL0 PHY1 (0x021b483c) = 0x4516054A
MPDGCTRL1 PHY1 (0x021b4840) = 0x0523047D

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x40404040
MPRDDLCTL PHY1 (0x021b4848) = 0x40404040

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x43414443
MPWRDLCTL PHY1 (0x021b4850) = 0x4633473E

Status registers, upper and lower bounds, for read DQS gating. 
MPDGHWST0 PHY0 (0x021b087c) = 0x03000040
MPDGHWST1 PHY0 (0x021b0880) = 0x02C00040
MPDGHWST2 PHY0 (0x021b0884) = 0x03000040
MPDGHWST3 PHY0 (0x021b0888) = 0x07C007C0
MPDGHWST0 PHY1 (0x021b487c) = 0x038A0001
MPDGHWST1 PHY1 (0x021b4880) = 0x03560001
MPDGHWST2 PHY1 (0x021b4884) = 0x033D0001
MPDGHWST3 PHY1 (0x021b4888) = 0x03630001

Centon MICU58PIA / CAP1066SO2048.01 (generic POS): 

Write leveling calibration completed, errcount: 0
MMDC_MPWLDECTRL0 after write level cal: 0x00120022
MMDC_MPWLDECTRL1 after write level cal: 0x017F0045
MMDC_MPWLDECTRL0 after write level cal: 0x0050013F
MMDC_MPWLDECTRL1 after write level cal: 0x00690118
Novena U-Boot > tmwcal
Start write leveling calibration 
.
Write leveling calibration completed, errcount: 0
MMDC_MPWLDECTRL0 after write level cal: 0x00120023
MMDC_MPWLDECTRL1 after write level cal: 0x017E0045
MMDC_MPWLDECTRL0 after write level cal: 0x00500141
MMDC_MPWLDECTRL1 after write level cal: 0x006A0118
Novena U-Boot > tmdel


Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x44001440
MPDGCTRL1 PHY0 (0x021b0840) = 0x0E000440
MPDGCTRL0 PHY1 (0x021b483c) = 0x45170555
MPDGCTRL1 PHY1 (0x021b4840) = 0x051F0479

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x40404040
MPRDDLCTL PHY1 (0x021b4848) = 0x40404040

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x43424544
MPWRDLCTL PHY1 (0x021b4850) = 0x36313339

Status registers, upper and lower bounds, for read DQS gating. 
MPDGHWST0 PHY0 (0x021b087c) = 0x03000040
MPDGHWST1 PHY0 (0x021b0880) = 0x02C00040
MPDGHWST2 PHY0 (0x021b0884) = 0x03000040
MPDGHWST3 PHY0 (0x021b0888) = 0x07C007C0
MPDGHWST0 PHY1 (0x021b487c) = 0x03950001
MPDGHWST1 PHY1 (0x021b4880) = 0x03570001
MPDGHWST2 PHY1 (0x021b4884) = 0x03390001
MPDGHWST3 PHY1 (0x021b4888) = 0x035F0001

SN001 Kingston 2-rank KVR16S11/4 cal, with new uboot (1/13): 

write starting at 10000000
checksum: 7ffd001e
read starting at 10000000
computed: 7ffd001e, readback: 7fe961b9
Start write leveling calibration 
.Write leveling calibration completed, errcount: 0
MMDC_MPWLDECTRL0 after write level cal: 0x002A002E
MMDC_MPWLDECTRL1 after write level cal: 0x0015004E
MMDC_MPWLDECTRL0 after write level cal: 0x00640150
MMDC_MPWLDECTRL1 after write level cal: 0x00680126
init cs0: 1 cs1: 1
cal cs0: 1 cs1: 0
db size: 2
Starting DQS gating calibration...
.errorcount: 0
DQS gating calibration completed, hit enter to proceed.
Starting read calibration...
intdel0: 40404040 / intdel1: 40404040
.errorcount: 0
Read calibration completed, hit enter to continue
Starting write calibration...
intdel0: 40404040 / intdel1: 40404040
.errorcount: 0
Write calibration completed, hit enter to continue
MMDC registers updated from calibration 

Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x437E041A
MPDGCTRL1 PHY0 (0x021b0840) = 0x03500445
MPDGCTRL0 PHY1 (0x021b483c) = 0x4473053B
MPDGCTRL1 PHY1 (0x021b4840) = 0x050D046A

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x45414642
MPRDDLCTL PHY1 (0x021b4848) = 0x4548424C

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x45414545
MPWRDLCTL PHY1 (0x021b4850) = 0x45324641

Status registers, upper and lower bounds, for read DQS gating. 
MPDGHWST0 PHY0 (0x021b087c) = 0x02DA0001
MPDGHWST1 PHY0 (0x021b0880) = 0x02BE0001
MPDGHWST2 PHY0 (0x021b0884) = 0x03050001
MPDGHWST3 PHY0 (0x021b0888) = 0x02900001
MPDGHWST0 PHY1 (0x021b487c) = 0x037B0001
MPDGHWST1 PHY1 (0x021b4880) = 0x03330001
MPDGHWST2 PHY1 (0x021b4884) = 0x032A0001
MPDGHWST3 PHY1 (0x021b4888) = 0x034D0001
errorcount: 0
init cs0: 1 cs1: 1
cal cs0: 1 cs1: 0
db size: 2
Starting DQS gating calibration...
.errorcount: 0
DQS gating calibration completed, hit enter to proceed.
Starting read calibration...
intdel0: 40404040 / intdel1: 40404040
.errorcount: 0
Read calibration completed, hit enter to continue
Starting write calibration...
intdel0: 40404040 / intdel1: 40404040
.errorcount: 0
Write calibration completed, hit enter to continue
MMDC registers updated from calibration 

Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x4401041B
MPDGCTRL1 PHY0 (0x021b0840) = 0x03530443
MPDGCTRL0 PHY1 (0x021b483c) = 0x4475053F
MPDGCTRL1 PHY1 (0x021b4840) = 0x050E046A

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x45424642
MPRDDLCTL PHY1 (0x021b4848) = 0x4548424C

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x45414545
MPWRDLCTL PHY1 (0x021b4850) = 0x45324641

Status registers, upper and lower bounds, for read DQS gating. 
MPDGHWST0 PHY0 (0x021b087c) = 0x02DB0001
MPDGHWST1 PHY0 (0x021b0880) = 0x02C10001
MPDGHWST2 PHY0 (0x021b0884) = 0x03030001
MPDGHWST3 PHY0 (0x021b0888) = 0x02930001
MPDGHWST0 PHY1 (0x021b487c) = 0x037F0001
MPDGHWST1 PHY1 (0x021b4880) = 0x03350001
MPDGHWST2 PHY1 (0x021b4884) = 0x032A0001
MPDGHWST3 PHY1 (0x021b4888) = 0x034E0001
errorcount: 0
write starting at 10000000
checksum: 7ffd001e
read starting at 10000000
computed: 7ffd001e, readback: 7ffd001e
### main_loop entered: bootdelay=1

1-rank calibrations

Kingston 1-rank (1GB magic DIMM) from HP craptop HP594907-HR1-ELFEU / 1GB 1Rx8 PC3-10600S-9-10-B1: 

Write leveling calibration completed, errcount: 0
MMDC_MPWLDECTRL0 after write level cal: 0x004B0055
MMDC_MPWLDECTRL1 after write level cal: 0x00700069
MMDC_MPWLDECTRL0 after write level cal: 0x0067010F
MMDC_MPWLDECTRL1 after write level cal: 0x0114011D
Novena U-Boot > tmwcal
Start write leveling calibration 
.
Write leveling calibration completed, errcount: 0
MMDC_MPWLDECTRL0 after write level cal: 0x004B0055
MMDC_MPWLDECTRL1 after write level cal: 0x00700069
MMDC_MPWLDECTRL0 after write level cal: 0x0067010F
MMDC_MPWLDECTRL1 after write level cal: 0x0114011F

Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x437D0413
MPDGCTRL1 PHY0 (0x021b0840) = 0x040F0416
MPDGCTRL0 PHY1 (0x021b483c) = 0x44570455
MPDGCTRL1 PHY1 (0x021b4840) = 0x045F0426

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x4C44434A
MPRDDLCTL PHY1 (0x021b4848) = 0x4B494151

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x34344139
MPWRDLCTL PHY1 (0x021b4850) = 0x3E2F4638

Status registers, upper and lower bounds, for read DQS gating. 
MPDGHWST0 PHY0 (0x021b087c) = 0x02D30001
MPDGHWST1 PHY0 (0x021b0880) = 0x02BD0001
MPDGHWST2 PHY0 (0x021b0884) = 0x02D60001
MPDGHWST3 PHY0 (0x021b0888) = 0x02CF0001
MPDGHWST0 PHY1 (0x021b487c) = 0x03150001
MPDGHWST1 PHY1 (0x021b4880) = 0x03170001
MPDGHWST2 PHY1 (0x021b4884) = 0x02E60001
MPDGHWST3 PHY1 (0x021b4888) = 0x031F0001
errorcount: 0

With new codebase integrated into u-boot (jan 13): 

MMDC_MPWLDECTRL0 after write level cal: 0x003F0046
MMDC_MPWLDECTRL1 after write level cal: 0x00660059
MMDC_MPWLDECTRL0 after write level cal: 0x005F0107
MMDC_MPWLDECTRL1 after write level cal: 0x00640115

Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x436D037D
MPDGCTRL1 PHY0 (0x021b0840) = 0x037F040D
MPDGCTRL0 PHY1 (0x021b483c) = 0x44500447
MPDGCTRL1 PHY1 (0x021b4840) = 0x04570421

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x48454244
MPRDDLCTL PHY1 (0x021b4848) = 0x474C434F

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x32304137
MPWRDLCTL PHY1 (0x021b4850) = 0x452C4637

Status registers, upper and lower bounds, for read DQS gating. 
MPDGHWST0 PHY0 (0x021b087c) = 0x02BD0001
MPDGHWST1 PHY0 (0x021b0880) = 0x02AD0001
MPDGHWST2 PHY0 (0x021b0884) = 0x02CD0001
MPDGHWST3 PHY0 (0x021b0888) = 0x02BF0001
MPDGHWST0 PHY1 (0x021b487c) = 0x03070001
MPDGHWST1 PHY1 (0x021b4880) = 0x03100001
MPDGHWST2 PHY1 (0x021b4884) = 0x02E10001
MPDGHWST3 PHY1 (0x021b4888) = 0x03170001

Errcount is zero, and the trivial write/read test seems to work with these parameters.

Note above that the errorcount is 0 on this run.

Micron CT25664BC1067.M8FMR:

Can't do write leveling calibration, use from kingston above. 

Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x440D0422
MPDGCTRL1 PHY0 (0x021b0840) = 0x0418041F
MPDGCTRL0 PHY1 (0x021b483c) = 0x4459045E
MPDGCTRL1 PHY1 (0x021b4840) = 0x0467042E

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x4A3F454B
MPRDDLCTL PHY1 (0x021b4848) = 0x464A424F

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x3636443F
MPWRDLCTL PHY1 (0x021b4850) = 0x42334A3D

Other Notes

Measurements performed using TDS5104B 1GHz oscilloscope with dual active P6245 probes:

  • probe 3 has about a -5% full scale offset (1.5V reads around 1.45V)
  • probe 4 is pretty much dead on

drive strength on A5 looks fine with 60 ohm setting (0x20)

setting of 0x38 improves margin by about 90mV. Tiny overshoot seen. slight improvement in slew rate

conclusion: set to 48 ohm, 0x28 --> looks best here, absolutely no overshoot, signal amplitude matched to clock

dqs7 measured on the dimm side of the termination resistor:

  • dimm->cpu rank 0, DQS7 0.36 - 1.19V swing, 830mv total. seems over-driven compared to clock, some reflection seen. in-phase with clock.
  • dimm->cpu rank 1 same effect
  • cpu->dimm rank 0, DQ7 0.45 - 1.1V swing, 650mV total. a bit cleaner. negative overshoot down to 0.22v seen on leading edge. 180 degrees out of phase with respect to clock.
  • cpu->dimm rank 1, same effect

DQS4 is seen as problematic in read/write tests, as evidenced by data patterns: 

Novena U-Boot > tmw.l 0xa0000000 0x0000ffff 0x400
Novena U-Boot > tmd.b 0xa0000000
a0000000: ff ff 00 00 3f ff 00 00 ff ff 00 00 d0 ff 00 00    ....?...........
a0000010: ff ff 00 00 ba ff 00 00 ff ff 00 00 f6 ff 00 00    ................

significantly, DQS4 is the very last DQS in the fly-by topology chain!

Handy Resources

Board layout files for SO-DIMMs. Looks like 90% of all SO-DIMMs use the reference design with very, very minor tweaks. There are basically two types of SO-DIMM layouts, one for single-rank, and one for dual-rank. The exception is Samsung, their low power DDR line has a novel layout. http://www.jedec.org/standards-documents/focus/memory-module-designs-dimms/DDR3/204-pin%20Unbuffered%20SODIMMs

SPD values

Kingston HP594907

1-rank 1GByte, calibration OK 

0000: 92 10 0b 03 02 11 00 01 03 52 01 08 0c 00 3e 00    .........R....>.
0010: 69 78 69 30 69 11 20 89 70 03 3c 3c 00 f0 83 81    ixi0i. .p.<<....
0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 21 00    ..............!.
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0070: 00 00 00 00 00 01 98 06 11 17 81 3a 84 08 1a c6    ...........:....
0080: 48 50 35 39 34 39 30 37 2d 48 52 31 2d 45 4c 46    HP594907-HR1-ELF
0090: 45 55 00 00 00 00 00 00 00 00 00 00 00 00 00 00    EU..............
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5a    ...............Z
00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

Crucial CT51264BC1067.M16FKD

2-rank 4Gbyte, calibration NG 

0000: 92 10 0b 03 03 19 00 09 03 52 01 08 0f 00 1e 00    .........R......
0010: 69 78 69 3c 69 11 2c 95 00 05 3c 3c 01 2c 82 05    ixi<i.,...<<.,..
0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 05 00    ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0070: 00 00 00 00 00 85 9b 00 0c 2f 00 00 00 00 41 e1    ........./....A.
0080: 43 54 35 31 32 36 34 42 43 31 30 36 37 2e 4d 31    CT51264BC1067.M1
0090: 36 46 4b 44 80 2c 00 00 00 00 00 00 00 00 00 00    6FKD.,..........
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
00c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
00d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
00e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
00f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................

Crucial CT25664BC1067.M8FMR=

1-rank 2GB, calibration NG 

0000: 92 10 0b 03 03 19 00 01 03 52 01 08 0f 00 1e 00    .........R......
0010: 69 78 69 3c 69 11 2c 95 00 05 3c 3c 01 2c 82 05    ixi<i.,...<<.,..
0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 01 00    ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0070: 00 00 00 00 00 85 9b 00 0c 2f 00 00 00 00 4e 59    ........./....NY
0080: 43 54 32 35 36 36 34 42 43 31 30 36 37 2e 4d 38    CT25664BC1067.M8
0090: 46 4d 52 00 80 2c 00 00 00 00 00 00 00 00 00 00    FMR..,..........
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
00c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
00d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
00e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
00f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................

Corsair CM3X4GSD1066

2-rank 4GB, calibration NG 

0000: 92 10 0b 03 03 19 00 09 03 52 01 08 0f 00 1c 00    .........R......
0010: 69 78 69 3c 69 11 2c 95 00 05 3c 3c 01 2c 83 0c    ixi<i.,...<<.,..
0020: 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 10 11 03 00    ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0070: 00 00 00 00 00 02 9e 01 00 00 00 00 00 00 5b 4a    ..............[J
0080: 43 4d 33 58 34 47 53 44 31 30 36 36 20 20 20 20    CM3X4GSD1066    
0090: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00      ..............
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

PNY Generic 4GB

2-rank 4GB, calibration NG. No brand or model number. 

0000: 92 10 0b 03 03 19 00 09 03 52 01 08 0f 00 1e 00    .........R......
0010: 69 78 69 3c 69 11 2c 95 00 05 3c 3c 01 2c 82 05    ixi<i.,...<<.,..
0020: 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 05 00    ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0070: 00 00 00 00 00 01 ba 00 00 00 00 00 00 00 07 06    ................
0080: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20                    
0090: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00      ..............
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

Samsung M473B5273DH0-YK0

2-rank 4GB, custom layout. Calibration NG. 

0000: 92 11 0b 03 03 19 02 09 03 11 01 08 0a 00 fe 00    ................
0010: 69 78 69 30 69 11 18 81 00 05 3c 3c 00 f0 83 01    ixi0i.....<<....
0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 0b 11 65 00    ..............e.
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0070: 00 00 00 00 00 80 ce 01 12 09 22 38 5d 69 32 fb    .........."8]i2.
0080: 4d 34 37 33 42 35 32 37 33 44 48 30 2d 59 4b 30    M473B5273DH0-YK0
0090: 20 20 00 00 80 ce 00 00 00 57 30 59 41 30 30 30      .......W0YA000
00a0: 01 00 01 00 00 00 00 00 00 00 00 00 00 00 00 01    ................
00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 30 37 00    .............07.
00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

Centon 2GB MICU58PIA

2-rank 2GB, calibration OK. 

0000: 92 01 0b 03 02 11 00 09 03 52 01 08 0f 00 1c 00    .........R......
0010: 69 78 69 3c 69 11 2c 95 70 03 3c 3c 01 2c 03 0d    ixi<i.,.p.<<.,..
0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 05 00    ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0070: 00 00 00 00 00 83 19 00 00 00 00 00 00 00 01 87    ................
0080: 4d 49 43 55 35 38 50 49 41 20 20 20 20 20 20 20    MICU58PIA       
0090: 20 20 00 00 00 00 43 45 4e 54 4f 4e 20 32 47 42      ....CENTON 2GB
00a0: 20 44 44 52 33 20 53 4f 44 49 4d 4d 20 20 20 20     DDR3 SODIMM    
00b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
00c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
00d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
00e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
00f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................

Kingston 99U5428-055

2-rank 4GB, calibration OK 

0000: 92 11 0b 03 03 19 00 09 03 52 01 08 0a 00 fe 00    .........R......
0010: 69 78 69 30 69 11 18 81 00 05 3c 3c 00 f0 83 81    ixi0i.....<<....
0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 65 00    ..............e.
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0070: 00 00 00 00 00 01 98 04 12 45 36 13 da 38 71 7b    .........E6..8q{
0080: 39 39 55 35 34 32 38 2d 30 35 35 2e 41 30 30 47    99U5428-055.A00G
0090: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00      ..............
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5a    ...............Z

Sample boot log

U-Boot 2012.10-rc1-00045-g7c35808-dirty (Feb 07 2013 - 04:10:45)

U-Boot code: 009073E0 -> 18000000  BSS: -> 180326C0
CPU:   Freescale i.MX6Q rev1.2 at 792 MHz
Reset cause: POR
Board: Novena Quattuor

SPD dump:
0000: 92 10 0b 03 03 19 00 09 03 52 01 08 0f 00 1e 00    .........R......
0010: 69 78 69 3c 69 11 2c 95 00 05 3c 3c 01 2c 82 05    ixi<i.,...<<.,..
0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 05 00    ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
0070: 00 00 00 00 00 85 9b 00 0c 2f 00 00 00 00 41 e1    ........./....A.
0080: 43 54 35 31 32 36 34 42 43 31 30 36 37 2e 4d 31    CT51264BC1067.M1
0090: 36 46 4b 44 80 2c 00 00 00 00 00 00 00 00 00 00    6FKD.,..........
00a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
00c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
00d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
00e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
00f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................

Raw DDR3 characteristics based on SPD:
  8 banks
  Individual chip density is 2048 Mib
  Rows: 15, Cols: 10
  Supports 1.5V operation.
  Module has 2 rank(s)
  Chips have a width of 8 bits
  Module width is 64 bits, no ECC
  Module capacity is 4 GiB
  DDR3-1066 speed rating detected
Derived optimal timing parameters, in 533MHz cycles:
  CAS latency: 7
  tWRmin: 8
  tRCDmin: 7
  tRRDmin: 4
  tRPmin: 7
  tRAS: 20
  tRC: 27
  tRFCmin: 86
  tWTRmin: 4
  tRTPmin: 4
  tFAW: 20
Info: no thermal sensor on-module
Vendor ID: 0x9b85
Module name: CT51264BC1067.M16F

Reprogramming DDR timings...
Original CTL: c41a0000
Optimal CTL: c41a0000
Original ASP: 0000003f
Optimal ASP: 0000003f
Original CFG0: babf79a5
Optimal CFG0: 55bf7814
Original CFG1: ff738f66
Optimal CFG1: db538f66
Original CFG2: 01ff00db
Optimal CFG2: 01ff00db

Reference read/write test prior to tuning
write starting at 10000000
checksum: 7ffd001e
read starting at 10000000
computed: 7ffd001e, readback: 683e0a03

Fly-by calibration
Start write leveling calibration 
.Write leveling calibration completed, errcount: 0
Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.
MMDC_MPWLDECTRL0 after write level cal: 0x001F001F
MMDC_MPWLDECTRL1 after write level cal: 0x001F001F
MMDC_MPWLDECTRL0 after write level cal: 0x00440044
MMDC_MPWLDECTRL1 after write level cal: 0x00440044
Fly-by calibration seems to have failed. Guessing values for wcal based on rank...

DQS delay calibration
init cs0: 1 cs1: 1
cal cs0: 1 cs1: 0
db size: 2
Starting DQS gating calibration...
.errorcount: 0
DQS gating calibration completed, hit enter to proceed.
Starting read calibration...
intdel0: 40404040 / intdel1: 40404040
.errorcount: 0
Read calibration completed, hit enter to continue
Starting write calibration...
intdel0: 40404040 / intdel1: 40404040
.errorcount: 0
Write calibration completed, hit enter to continue
MMDC registers updated from calibration 

Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x46030623
MPDGCTRL1 PHY0 (0x021b0840) = 0x054F0623
MPDGCTRL0 PHY1 (0x021b483c) = 0x4677073B
MPDGCTRL1 PHY1 (0x021b4840) = 0x0704065E

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x463E4447
MPRDDLCTL PHY1 (0x021b4848) = 0x48444049

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x463F4641
MPWRDLCTL PHY1 (0x021b4850) = 0x43364741

Status registers, upper and lower bounds, for read DQS gating. 
MPDGHWST0 PHY0 (0x021b087c) = 0x03E30001
MPDGHWST1 PHY0 (0x021b0880) = 0x03C30001
MPDGHWST2 PHY0 (0x021b0884) = 0x03E30001
MPDGHWST3 PHY0 (0x021b0888) = 0x038F0001
MPDGHWST0 PHY1 (0x021b487c) = 0x047B0001
MPDGHWST1 PHY1 (0x021b4880) = 0x04370001
MPDGHWST2 PHY1 (0x021b4884) = 0x041E0001
MPDGHWST3 PHY1 (0x021b4888) = 0x04440001
errorcount: 0
init cs0: 1 cs1: 1
cal cs0: 1 cs1: 0
db size: 2
Starting DQS gating calibration...
.errorcount: 0
DQS gating calibration completed, hit enter to proceed.
Starting read calibration...
intdel0: 40404040 / intdel1: 40404040
.errorcount: 0
Read calibration completed, hit enter to continue
Starting write calibration...
intdel0: 40404040 / intdel1: 40404040
.errorcount: 0
Write calibration completed, hit enter to continue
MMDC registers updated from calibration 

Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x46030623
MPDGCTRL1 PHY0 (0x021b0840) = 0x05500623
MPDGCTRL0 PHY1 (0x021b483c) = 0x4677073A
MPDGCTRL1 PHY1 (0x021b4840) = 0x0704065E

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x463E4447
MPRDDLCTL PHY1 (0x021b4848) = 0x4844404A

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x463F4641
MPWRDLCTL PHY1 (0x021b4850) = 0x43374741

Status registers, upper and lower bounds, for read DQS gating. 
MPDGHWST0 PHY0 (0x021b087c) = 0x03E30001
MPDGHWST1 PHY0 (0x021b0880) = 0x03C30001
MPDGHWST2 PHY0 (0x021b0884) = 0x03E30001
MPDGHWST3 PHY0 (0x021b0888) = 0x03900001
MPDGHWST0 PHY1 (0x021b487c) = 0x047A0001
MPDGHWST1 PHY1 (0x021b4880) = 0x04370001
MPDGHWST2 PHY1 (0x021b4884) = 0x041E0001
MPDGHWST3 PHY1 (0x021b4888) = 0x04440001
errorcount: 0

Reference read/write test post-tuning
write starting at 10000000
checksum: 7ffd001e
read starting at 10000000
computed: 7ffd001e, readback: 7ffd001e
ddrSPD.capacity: 00008000
Ramsize according to SPD: f0000000
Set gd->ram_size to f0000000
monitor len: 1772B2E0
ramsize: F0000000
TLB table at: ffff0000
Top of RAM usable for U-Boot at: ffff0000
Reserving 10248k for malloc() at: ff5ee000
Reserving 32 Bytes for Board Info at: ff5edfe0
Reserving 136 Bytes for Global Data at: ff5edf58
New Stack Pointer is: ff5edf48
RAM Configuration:
Bank #0: 10000000 3.8 GiB
relocation Offset is: 00000000
_TEXT_BASE: 009073e0
addr_sp: ff5edf48
monitor flash len: 0002E0C8
Now running in RAM - U-Boot at: 009073e0
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
board_mmc_getcd(): esdhc_base 0x02198000
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Hit any key to stop autoboot:  0 
board_mmc_getcd(): esdhc_base 0x02198000
mmc0 is current device
board_mmc_getcd(): esdhc_base 0x02198000
board_mmc_getcd(): esdhc_base 0x02198000
reading boot.scr

188 bytes read
Running bootscript from mmc ...
## Executing script at 10800000
board_mmc_getcd(): esdhc_base 0x02198000
reading uImage-novena.bin

3887512 bytes read
board_mmc_getcd(): esdhc_base 0x02198000
reading uImage-novena.dtb

17840 bytes read
## Booting kernel from Legacy Image at 12000000 ...
   Image Name:   Angstrom/3.6.0+r8+git/novena
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    3887448 Bytes = 3.7 MiB
   Load Address: 10008000
   Entry Point:  10008000
   Verifying Checksum ... OK
## Flattened Device Tree blob at 11ff0000
   Booting using the fdt blob at 0x11ff0000
   Loading Kernel Image ... OK
OK
   Using Device Tree in place at 11ff0000, end 11ff75af

Starting kernel ...
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